Simulation Results: sram_ctrl/main

 
19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.25 %
  • code
  • 96.30 %
  • assert
  • 96.46 %
  • func
  • 96.00 %
  • block
  • 95.47 %
  • line
  • 96.07 %
  • branch
  • 93.03 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 9.000s 5146.607us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.000s 17.158us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 15.161us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 3.000s 2249.932us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 22.170us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 1391.247us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 15.161us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 22.170us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 272.000s 98867.281us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 124.000s 2438.088us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 45.000s 4935.874us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 300.000s 8536.846us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 174.000s 22473.092us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 104.000s 27294.529us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 63.000s 14060.717us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 68.000s 117110.793us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 10.000s 3124.409us 5 5 100.00
sram_ctrl_partial_access_b2b 439.000s 19738.837us 5 5 100.00
max_throughput 5 15 33.33
sram_ctrl_max_throughput 8.000s 10943.568us 0 5 0.00
sram_ctrl_throughput_w_partial_write 7.000s 1398.663us 5 5 100.00
sram_ctrl_throughput_w_readback 7.000s 673.671us 0 5 0.00
regwen 5 5 100.00
sram_ctrl_regwen 19.000s 5185.370us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 4.000s 1526.877us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 754.000s 126914.859us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 39.570us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.000s 572.066us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.000s 572.066us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.000s 17.158us 5 5 100.00
sram_ctrl_csr_rw 2.000s 15.161us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 22.170us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 46.259us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.000s 17.158us 5 5 100.00
sram_ctrl_csr_rw 2.000s 15.161us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 22.170us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 46.259us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 49.000s 29356.454us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 5.000s 1405.078us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 616.171us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 1405.078us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 616.171us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 19.000s 5185.370us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 19.000s 5185.370us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 15.161us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 68.000s 117110.793us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 68.000s 117110.793us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 68.000s 117110.793us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 63.000s 14060.717us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 11.000s 11037.279us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 49.000s 29356.454us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 8.000s 1389.723us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 9.000s 5146.607us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 9.000s 5146.607us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 68.000s 117110.793us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 1405.078us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 63.000s 14060.717us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 1405.078us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1405.078us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 9.000s 5146.607us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1405.078us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 61.000s 1222.912us 5 5 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 68354261436083380285310022979948561919598853180950573447828978972089515902903 102
UVM_FATAL @ 1931785255 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 1931785255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 17760641250626528584665407431811871056081352665520781839180109386273487883205 102
UVM_FATAL @ 673942797 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 673942797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 59040743771999624094290915041786199757510124196815068615612805940124576992291 102
UVM_FATAL @ 674818093 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 674818093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 112137218751863648639666985222278747545911900793233417193065276070118358875901 102
UVM_FATAL @ 667226754 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 667226754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 81140621863307558408280096289834409534910537263558186344826778922098304383577 102
UVM_FATAL @ 10943567697 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 10943567697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 70430867277860480181239772781765995664806526498922331546437326361062358305329 102
UVM_FATAL @ 7303299954 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 7303299954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 61896994079317325392080311871417574371080548296804683312960195339068041907037 102
UVM_FATAL @ 1990532051 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 1990532051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 12090111065883136584733289738399676788680431227342329819022331295153464478768 102
UVM_FATAL @ 673671177 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 673671177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 109468629200093603289867030741048099909023838340915254268767319695440827892186 102
UVM_FATAL @ 3455794815 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 3455794815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 67784539575953899188254608560636048738314161535310929731690690658501477837397 102
UVM_FATAL @ 1647636972 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 1647636972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---