Simulation Results

Simulation Results: sram_ctrl/ret

19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.31 %

code
83.49 %

assert
96.43 %

func
97.00 %

block
94.01 %

line
95.19 %

branch
89.83 %

toggle
82.28 %

FSM
66.67 %

Validation stages

V1		95.71%
V2		94.21%
V2S		100.00%
V3		100.00%

67/70 passed

95.71 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				5	5	100.00
	sram_ctrl_smoke	3.000s	72.792us	5	5	100.00
csr_hw_reset				5	5	100.00
	sram_ctrl_csr_hw_reset	2.000s	148.345us	5	5	100.00
csr_rw				20	20	100.00
	sram_ctrl_csr_rw	2.000s	11.138us	20	20	100.00
csr_bit_bash				5	5	100.00
	sram_ctrl_csr_bit_bash	3.000s	82.784us	5	5	100.00
csr_aliasing				5	5	100.00
	sram_ctrl_csr_aliasing	2.000s	15.790us	5	5	100.00
csr_mem_rw_with_rand_reset				17	20	85.00
	sram_ctrl_csr_mem_rw_with_rand_reset	2.000s	170.853us	17	20	85.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sram_ctrl_csr_rw	2.000s	11.138us	20	20	100.00
	sram_ctrl_csr_aliasing	2.000s	15.790us	5	5	100.00
mem_walk				5	5	100.00
	sram_ctrl_mem_walk	11.000s	1141.217us	5	5	100.00
mem_partial_access				5	5	100.00
	sram_ctrl_mem_partial_access	5.000s	288.610us	5	5	100.00

179/190 passed

94.21 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				5	5	100.00
	sram_ctrl_multiple_keys	14.000s	522.374us	5	5	100.00
stress_pipeline				5	5	100.00
	sram_ctrl_stress_pipeline	293.000s	5088.487us	5	5	100.00
bijection				5	5	100.00
	sram_ctrl_bijection	9.000s	3719.554us	5	5	100.00
access_during_key_req				5	5	100.00
	sram_ctrl_access_during_key_req	22.000s	676.782us	5	5	100.00
lc_escalation				5	5	100.00
	sram_ctrl_lc_escalation	9.000s	3724.623us	5	5	100.00
executable				5	5	100.00
	sram_ctrl_executable	14.000s	10271.576us	5	5	100.00
partial_access				10	10	100.00
	sram_ctrl_partial_access	3.000s	767.472us	5	5	100.00
	sram_ctrl_partial_access_b2b	328.000s	35306.442us	5	5	100.00
max_throughput				5	15	33.33
	sram_ctrl_max_throughput	2.000s	22.477us	0	5	0.00
	sram_ctrl_throughput_w_partial_write	2.000s	63.425us	5	5	100.00
	sram_ctrl_throughput_w_readback	2.000s	103.938us	0	5	0.00
regwen				5	5	100.00
	sram_ctrl_regwen	9.000s	2176.226us	5	5	100.00
ram_cfg				5	5	100.00
	sram_ctrl_ram_cfg	2.000s	32.318us	5	5	100.00
stress_all				5	5	100.00
	sram_ctrl_stress_all	33.000s	2366.277us	5	5	100.00
alert_test				49	50	98.00
	sram_ctrl_alert_test	2.000s	18.858us	49	50	98.00
tl_d_oob_addr_access				20	20	100.00
	sram_ctrl_tl_errors	4.000s	235.314us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sram_ctrl_tl_errors	4.000s	235.314us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sram_ctrl_csr_hw_reset	2.000s	148.345us	5	5	100.00
	sram_ctrl_csr_rw	2.000s	11.138us	20	20	100.00
	sram_ctrl_csr_aliasing	2.000s	15.790us	5	5	100.00
	sram_ctrl_same_csr_outstanding	2.000s	22.343us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sram_ctrl_csr_hw_reset	2.000s	148.345us	5	5	100.00
	sram_ctrl_csr_rw	2.000s	11.138us	20	20	100.00
	sram_ctrl_csr_aliasing	2.000s	15.790us	5	5	100.00
	sram_ctrl_same_csr_outstanding	2.000s	22.343us	20	20	100.00

V2S

95/95 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	4.000s	387.844us	20	20	100.00
tl_intg_err				25	25	100.00
	sram_ctrl_tl_intg_err	3.000s	347.591us	20	20	100.00
	sram_ctrl_sec_cm	5.000s	659.211us	5	5	100.00
prim_count_check				5	5	100.00
	sram_ctrl_sec_cm	5.000s	659.211us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	sram_ctrl_tl_intg_err	3.000s	347.591us	20	20	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	sram_ctrl_regwen	9.000s	2176.226us	5	5	100.00
sec_cm_readback_config_regwen				5	5	100.00
	sram_ctrl_regwen	9.000s	2176.226us	5	5	100.00
sec_cm_exec_config_regwen				20	20	100.00
	sram_ctrl_csr_rw	2.000s	11.138us	20	20	100.00
sec_cm_exec_config_mubi				5	5	100.00
	sram_ctrl_executable	14.000s	10271.576us	5	5	100.00
sec_cm_exec_intersig_mubi				5	5	100.00
	sram_ctrl_executable	14.000s	10271.576us	5	5	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				5	5	100.00
	sram_ctrl_executable	14.000s	10271.576us	5	5	100.00
sec_cm_lc_escalate_en_intersig_mubi				5	5	100.00
	sram_ctrl_lc_escalation	9.000s	3724.623us	5	5	100.00
sec_cm_prim_ram_ctrl_mubi				5	5	100.00
	sram_ctrl_mubi_enc_err	2.000s	140.046us	5	5	100.00
sec_cm_mem_integrity				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	4.000s	387.844us	20	20	100.00
sec_cm_mem_readback				5	5	100.00
	sram_ctrl_readback_err	2.000s	40.943us	5	5	100.00
sec_cm_mem_scramble				5	5	100.00
	sram_ctrl_smoke	3.000s	72.792us	5	5	100.00
sec_cm_addr_scramble				5	5	100.00
	sram_ctrl_smoke	3.000s	72.792us	5	5	100.00
sec_cm_instr_bus_lc_gated				5	5	100.00
	sram_ctrl_executable	14.000s	10271.576us	5	5	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				5	5	100.00
	sram_ctrl_sec_cm	5.000s	659.211us	5	5	100.00
sec_cm_key_global_esc				5	5	100.00
	sram_ctrl_lc_escalation	9.000s	3724.623us	5	5	100.00
sec_cm_key_local_esc				5	5	100.00
	sram_ctrl_sec_cm	5.000s	659.211us	5	5	100.00
sec_cm_init_ctr_redun				5	5	100.00
	sram_ctrl_sec_cm	5.000s	659.211us	5	5	100.00
sec_cm_scramble_key_sideload				5	5	100.00
	sram_ctrl_smoke	3.000s	72.792us	5	5	100.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	sram_ctrl_sec_cm	5.000s	659.211us	5	5	100.00

5/5 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				5	5	100.00
	sram_ctrl_stress_all_with_rand_reset	51.000s	4735.664us	5	5	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [] vs []) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value:
	sram_ctrl_csr_mem_rw_with_rand_reset	27746621605236552280759963804345527122387296294211293808253750557889850190109	88	UVM_ERROR @ 88082338 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (11 [0xb] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9 UVM_INFO @ 88082338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_csr_mem_rw_with_rand_reset	17520857922634918392798988354720206805095427321318367189647705349628847171537	94	UVM_ERROR @ 31884665 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9 UVM_INFO @ 31884665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [] vs []) Regname: sram_ctrl_regs_reg_block.status reset value:
	sram_ctrl_csr_mem_rw_with_rand_reset	67921690936283749470352922325311776037121124411503259004911444961333681173711	88	UVM_ERROR @ 368915669 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0 UVM_INFO @ 368915669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-:], 'b0}) <= ; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
	sram_ctrl_max_throughput	66505274496502352867489244193614604657015091125746699703259900533588142684214	102	UVM_FATAL @ 22476887 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 22476887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	19930239682402698564595182458615920658777526890278963349981699795156422469300	102	UVM_FATAL @ 103937944 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 103937944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_max_throughput	89018585458675937953633866057683608000817584495215814247730901525500313612762	102	UVM_FATAL @ 87928504 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 87928504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	9313734999690652309710893607515222516681454769819084643370869670800530789552	102	UVM_FATAL @ 166682660 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 166682660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_max_throughput	111038766405268547818337635578072186320813037593944108603402697258331349177332	102	UVM_FATAL @ 121959456 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 121959456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	4969762468626698522252800757959671784982815136980786255586070247777629935920	102	UVM_FATAL @ 90524474 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 90524474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_max_throughput	50543126864602173540691315037218967978922993095638999218394421275553210205299	102	UVM_FATAL @ 89306957 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 89306957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	9671520158856319296037166779669229386326709555488191541164134875242718970766	102	UVM_FATAL @ 33047765 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 33047765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_max_throughput	114507241642001454619033567992456392718362573762862908955537924029555027930410	102	UVM_FATAL @ 37887150 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 37887150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_throughput_w_readback	48929284685148690671289307151414933366552884287349579573516769043395859208769	102	UVM_FATAL @ 115822213 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed! UVM_INFO @ 115822213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_/rtl/tlul_assert.sv,319): Assertion noOutstandingReqsAtEndOfSim_A has failed
	sram_ctrl_alert_test	7179508422782669267936464984843233175796828871384101636481180473909441003861	122	xmsim: E,ASRTST (/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv,319): (time 33579117 PS) Assertion tb.dut.tlul_assert_device_regs.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A has failed xmsim: W,SLFINV: Call to process::self() from invalid process; returning null. xmsim: W,SLFINV: Call to process::self() from invalid process; returning null. xmsim: W,SLFINV: Call to process::self() from invalid process; returning null. xmsim: *W,SLFINV: Call to process::self() from invalid process; returning null.