Simulation Results: alert_handler

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.14 %
  • code
  • 98.84 %
  • assert
  • 98.92 %
  • func
  • 99.66 %
  • line
  • 99.99 %
  • branch
  • 99.99 %
  • cond
  • 97.52 %
  • toggle
  • 96.72 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
96.20%
V2S
99.25%
V3
58.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
alert_handler_smoke 88.840s 4321.278us 50 50 100.00
csr_hw_reset 5 5 100.00
alert_handler_csr_hw_reset 8.750s 208.239us 5 5 100.00
csr_rw 20 20 100.00
alert_handler_csr_rw 14.120s 985.882us 20 20 100.00
csr_bit_bash 5 5 100.00
alert_handler_csr_bit_bash 523.080s 9969.904us 5 5 100.00
csr_aliasing 5 5 100.00
alert_handler_csr_aliasing 316.250s 9484.092us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
alert_handler_csr_mem_rw_with_rand_reset 15.000s 193.195us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
alert_handler_csr_rw 14.120s 985.882us 20 20 100.00
alert_handler_csr_aliasing 316.250s 9484.092us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 50 50 100.00
alert_handler_esc_alert_accum 329.580s 6723.922us 50 50 100.00
esc_timeout 50 50 100.00
alert_handler_esc_intr_timeout 95.390s 1289.168us 50 50 100.00
entropy 50 50 100.00
alert_handler_entropy 3542.190s 340296.783us 50 50 100.00
sig_int_fail 49 50 98.00
alert_handler_sig_int_fail 67.440s 847.689us 49 50 98.00
clk_skew 50 50 100.00
alert_handler_smoke 88.840s 4321.278us 50 50 100.00
random_alerts 50 50 100.00
alert_handler_random_alerts 82.310s 3818.530us 50 50 100.00
random_classes 50 50 100.00
alert_handler_random_classes 96.900s 8253.657us 50 50 100.00
ping_timeout 27 50 54.00
alert_handler_ping_timeout 681.290s 207784.873us 27 50 54.00
lpg 97 100 97.00
alert_handler_lpg 3031.720s 348087.877us 49 50 98.00
alert_handler_lpg_stub_clk 3212.790s 246572.448us 48 50 96.00
stress_all 50 50 100.00
alert_handler_stress_all 4368.930s 82431.047us 50 50 100.00
alert_handler_entropy_stress_test 20 20 100.00
alert_handler_entropy_stress 80.540s 5589.802us 20 20 100.00
alert_handler_alert_accum_saturation 20 20 100.00
alert_handler_alert_accum_saturation 5.350s 50.822us 20 20 100.00
intr_test 50 50 100.00
alert_handler_intr_test 2.400s 12.263us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
alert_handler_tl_errors 36.060s 4468.574us 20 20 100.00
tl_d_illegal_access 20 20 100.00
alert_handler_tl_errors 36.060s 4468.574us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
alert_handler_csr_hw_reset 8.750s 208.239us 5 5 100.00
alert_handler_csr_rw 14.120s 985.882us 20 20 100.00
alert_handler_csr_aliasing 316.250s 9484.092us 5 5 100.00
alert_handler_same_csr_outstanding 61.810s 2946.418us 20 20 100.00
tl_d_partial_access 50 50 100.00
alert_handler_csr_hw_reset 8.750s 208.239us 5 5 100.00
alert_handler_csr_rw 14.120s 985.882us 20 20 100.00
alert_handler_csr_aliasing 316.250s 9484.092us 5 5 100.00
alert_handler_same_csr_outstanding 61.810s 2946.418us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
alert_handler_shadow_reg_errors 404.930s 5960.421us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
alert_handler_shadow_reg_errors 404.930s 5960.421us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
alert_handler_shadow_reg_errors 404.930s 5960.421us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
alert_handler_shadow_reg_errors 404.930s 5960.421us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
alert_handler_shadow_reg_errors_with_csr_rw 1469.940s 37752.259us 20 20 100.00
tl_intg_err 25 25 100.00
alert_handler_sec_cm 43.760s 786.199us 5 5 100.00
alert_handler_tl_intg_err 98.500s 2401.386us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
alert_handler_tl_intg_err 98.500s 2401.386us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
alert_handler_shadow_reg_errors 404.930s 5960.421us 20 20 100.00
sec_cm_ping_timer_config_regwen 50 50 100.00
alert_handler_smoke 88.840s 4321.278us 50 50 100.00
sec_cm_alert_config_regwen 50 50 100.00
alert_handler_smoke 88.840s 4321.278us 50 50 100.00
sec_cm_alert_loc_config_regwen 50 50 100.00
alert_handler_smoke 88.840s 4321.278us 50 50 100.00
sec_cm_class_config_regwen 50 50 100.00
alert_handler_smoke 88.840s 4321.278us 50 50 100.00
sec_cm_alert_intersig_diff 49 50 98.00
alert_handler_sig_int_fail 67.440s 847.689us 49 50 98.00
sec_cm_lpg_intersig_mubi 49 50 98.00
alert_handler_lpg 3031.720s 348087.877us 49 50 98.00
sec_cm_esc_intersig_diff 49 50 98.00
alert_handler_sig_int_fail 67.440s 847.689us 49 50 98.00
sec_cm_alert_rx_intersig_bkgn_chk 50 50 100.00
alert_handler_entropy 3542.190s 340296.783us 50 50 100.00
sec_cm_esc_tx_intersig_bkgn_chk 50 50 100.00
alert_handler_entropy 3542.190s 340296.783us 50 50 100.00
sec_cm_esc_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 43.760s 786.199us 5 5 100.00
sec_cm_ping_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 43.760s 786.199us 5 5 100.00
sec_cm_esc_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 43.760s 786.199us 5 5 100.00
sec_cm_ping_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 43.760s 786.199us 5 5 100.00
sec_cm_esc_timer_fsm_global_esc 5 5 100.00
alert_handler_sec_cm 43.760s 786.199us 5 5 100.00
sec_cm_accu_ctr_redun 5 5 100.00
alert_handler_sec_cm 43.760s 786.199us 5 5 100.00
sec_cm_esc_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 43.760s 786.199us 5 5 100.00
sec_cm_ping_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 43.760s 786.199us 5 5 100.00
sec_cm_ping_timer_lfsr_redun 5 5 100.00
alert_handler_sec_cm 43.760s 786.199us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 29 50 58.00
alert_handler_stress_all_with_rand_reset 658.890s 20375.135us 29 50 58.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 14428422585099547899338037027903885076242984224489536336661241933352332419788 102
UVM_ERROR @ 9619371316 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 9619371316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 54301108187775409377950910363305168033670803596577848315233448172488169867916 84
UVM_ERROR @ 12375121388 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 12375121388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 55070658714341536180242409245409816241204789245992488396029886339213643758278 156
UVM_ERROR @ 51669363894 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 51669363894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 109992222028003879642124736056267000904314931755377175763410296216329724461485 153
UVM_ERROR @ 18589077178 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 18589077178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 22402295268965725187183529954567870641855928108918146774884890861511036921266 123
UVM_ERROR @ 7010687766 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 7010687766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 21597399169120875066065947206902839588032898597099368396404818250739430976981 117
UVM_ERROR @ 13505771634 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 13505771634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 88042399902281017801034482363927696496278198803273728301708313773206327923041 126
UVM_ERROR @ 7781630439 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 7781630439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 20840404182384806976164140580011548618233716790350708600087534044616154931086 120
UVM_ERROR @ 8128140946 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 8128140946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 63912006268579039826857586267853536135102708417161584845528534397330806844279 105
UVM_ERROR @ 10735508208 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 10735508208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 59699360142521885845332582388632724553274936550818501641611539537678513196274 90
UVM_ERROR @ 28260098745 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 28260098745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 107212832430441946514630865679375891870782028956590990255345105873713507539586 87
UVM_ERROR @ 3939873082 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 3939873082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 27939020891266007695234295187538027076553995495503161373390516770037162165506 90
UVM_ERROR @ 3055744879 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 3055744879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 61113911709092192677552795077906719456826284359016210419021976478616610593149 117
UVM_ERROR @ 5078177645 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 5078177645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 99967766409463470716798028051195081523622596231605369208221408393111599231236 87
UVM_ERROR @ 2963357344 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 2963357344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 26528810913563261608792783812433710772442403627233012122578749808335489524716 87
UVM_ERROR @ 2962776800 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 2962776800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 76822451985651988083253058026256471162742623541514504784379571228648580200988 93
UVM_ERROR @ 8350211767 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 8350211767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 10063859943538311248845307801018191748890382315434657762393095293477643698896 108
UVM_ERROR @ 6990262983 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 6990262983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 74814661885066682475306255650445729517374011993339836308352235635834553623421 91
UVM_ERROR @ 6226301924 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 6226301924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 81953525248415032689736634740528046695230926167073152702678464755727167476705 93
UVM_ERROR @ 3140233455 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 3140233455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state
alert_handler_sig_int_fail 42661366988562020000005151432820684240539791919441968249901494763414452790488 83
UVM_ERROR @ 669176859 ps: (alert_handler_scoreboard.sv:490) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 6 [0x6]) reg name: alert_handler_reg_block.classa_state
UVM_INFO @ 669176859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model.
alert_handler_ping_timeout 41277610727596617680983044495512103513866287560628934459222377266614682215966 81
UVM_ERROR @ 692057451 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 692057451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 4402320425414356745013211198263252121671635022797649065906329648165622521392 80
UVM_ERROR @ 2992562420 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 2992562420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 84146305391574305434667777659122952482321818733224270154887569877523099595278 80
UVM_ERROR @ 395518125 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 395518125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 66506821651548183466178466389585435403293119943384044405628892994350237726490 80
UVM_ERROR @ 364799936 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 364799936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 109032840623945761824501414937187709622695406112956688033328305364046356893657 93
UVM_ERROR @ 669223678 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 669223678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 103871841911193963879259103355127385992701903906077953996909856074520803430422 138
UVM_ERROR @ 1787614909 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1787614909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 22055496770209494740337226404613979725774322805897954011193717887957337793503 154
UVM_ERROR @ 4999811284 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4999811284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 112765474937221200809637376031385262373649504464108270318831517264872691481331 134
UVM_ERROR @ 5456448882 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5456448882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 82484266701173100182895834682244624668251860901086708415899361546267488258449 83
UVM_ERROR @ 500024967 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 500024967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 18476886437517555798042286896811799924437964249363266083446905238618330749456 95
UVM_ERROR @ 1021584936 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1021584936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 113614402260836331171765597281670561346502787886970875634260364097271306894319 114
UVM_ERROR @ 6273121882 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6273121882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 99558339354781602370545941091541456145025219312625947632648486453403569904913 116
UVM_ERROR @ 1938299391 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1938299391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 14057395891928779423338310915099335877706300519114475232930640847687567830044 102
UVM_ERROR @ 919514440 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 919514440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 70923235583608739867859265114078508549651414825670951905153951570144541401439 112
UVM_ERROR @ 7489642207 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7489642207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 94562701928253622286010427400716462033323453562951578803616412491275791660466 133
UVM_ERROR @ 1537051706 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1537051706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 37168817385680751267996040892097479137726945896321278140528235989493267193271 127
UVM_ERROR @ 2157266556 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2157266556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 62440417373537752298273820752322789371054359082604755343978587822215728564577 83
UVM_ERROR @ 2064877469 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2064877469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 19119095159955706729455200576809178251205526188021756404927220074752984143372 116
UVM_ERROR @ 20294227505 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 20294227505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 29141928480475311929851775680339825174661414927997840490453480094295401972413 173
UVM_ERROR @ 7831056480 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7831056480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 20418332064513969919520477151929706904074901752966068365239798799069908182842 106
UVM_ERROR @ 11509077935 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11509077935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 106779967993556820642243802809653337610394503554227357066585047541612270915668 149
UVM_ERROR @ 22809309158 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 22809309158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 40740266440534605102014900835924938212999054334869334043749214894377390994763 165
UVM_ERROR @ 6865434717 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6865434717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 45755494751285253354581927099728727721345954425679606685314937856407544172826 143
UVM_ERROR @ 1671017775 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1671017775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 26625663222090566162694888359165633442435325494447129982032370429020636279140 217
UVM_ERROR @ 10208529905 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10208529905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 4235210324033469046358792855667684673503144930537892563081172735584082293575 83
UVM_ERROR @ 106603514 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 106603514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.loc_alert_cause_*
alert_handler_lpg 57380402392635889715980858576332577451981022791461693231448362748093556433968 80
UVM_ERROR @ 8945061276 ps: (alert_handler_scoreboard.sv:490) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: alert_handler_reg_block.loc_alert_cause_0
UVM_INFO @ 8945061276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_lpg_stub_clk 21224122446785414659975750244135073556729219139708698858202617388543609153538 80
UVM_ERROR @ 111586137775 ps: (alert_handler_scoreboard.sv:490) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: alert_handler_reg_block.loc_alert_cause_0
UVM_INFO @ 111586137775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
alert_handler_lpg_stub_clk 44194124664178592216599730332102044493607842708217064781507323692756527123680 80
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---