Simulation Results: dma

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.66 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 77.82 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
99.48%
V2S
100.00%
unmapped
93.55%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 32.000s 456.959us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 32.000s 316.490us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 35.000s 320.609us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 2.000s 15.431us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 2.000s 20.580us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 15.000s 1035.081us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 9.000s 1181.861us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 3.000s 31.394us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 2.000s 20.580us 20 20 100.00
dma_csr_aliasing 9.000s 1181.861us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 74.000s 10282.692us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 655.000s 832685.984us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 698.000s 742031.069us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 698.000s 742031.069us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 655.000s 832685.984us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 1489.000s 863951.483us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 698.000s 742031.069us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 26.000s 472.110us 5 5 100.00
dma_stress_all 2 3 66.67
dma_stress_all 311.000s 83179.681us 2 3 66.67
alert_test 50 50 100.00
dma_alert_test 2.000s 26.155us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 2.000s 11.110us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 4.000s 174.216us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 4.000s 174.216us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 2.000s 15.431us 5 5 100.00
dma_csr_rw 2.000s 20.580us 20 20 100.00
dma_csr_aliasing 9.000s 1181.861us 5 5 100.00
dma_same_csr_outstanding 3.000s 75.285us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 2.000s 15.431us 5 5 100.00
dma_csr_rw 2.000s 20.580us 20 20 100.00
dma_csr_aliasing 9.000s 1181.861us 5 5 100.00
dma_same_csr_outstanding 3.000s 75.285us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 29.000s 181.393us 5 5 100.00
dma_generic_stress 1489.000s 863951.483us 5 5 100.00
dma_handshake_stress 698.000s 742031.069us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 11.000s 298.731us 15 15 100.00
tl_intg_err 25 25 100.00
dma_sec_cm 2.000s 37.278us 5 5 100.00
dma_tl_intg_err 4.000s 103.862us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 29 31 93.55
dma_short_transfer 166.000s 200000.000us 24 25 96.00
dma_longer_transfer 6.000s 530.801us 5 5 100.00
dma_stress_all_with_rand_reset 4.000s 1315.469us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 109398907714705168686527565664996096877470271119899293080959599118313903380366 95
UVM_ERROR @ 1315468679ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1315468679ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ *ps: (dma_scoreboard.sv:698) [scoreboard] Check failed curr_intr == exp_intr (* [*] vs * [*]) Unexpected state of interrupt signals (Mismatched: ChunkDone )
dma_stress_all 30605854150555788744381530550367049854335402723255661693149196197853763145617 269
UVM_ERROR @ 11927200575ps: (dma_scoreboard.sv:698) [uvm_test_top.env.scoreboard] Check failed curr_intr == exp_intr (0 [0x0] vs 2 [0x2]) Unexpected state of interrupt signals (Mismatched: ChunkDone )
UVM_INFO @ 11927200575ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ *ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of *ps hit, indicating a probable testbench issue
dma_short_transfer 52077021310823914443662803887223132108483384147476657605320297246578377923920 2185
UVM_FATAL @ 200000000000ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---