Simulation Results: edn/edn0

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.42 %
  • code
  • 95.60 %
  • assert
  • 97.61 %
  • func
  • 93.06 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.02 %
  • toggle
  • 97.17 %
  • FSM
  • 91.40 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
84.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.370s 17.451us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.280s 15.470us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.360s 24.214us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.370s 139.183us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.980s 67.726us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 2.060s 69.880us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.360s 24.214us 20 20 100.00
edn_csr_aliasing 1.980s 67.726us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 173.920s 14579.981us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 173.920s 14579.981us 300 300 100.00
genbits 300 300 100.00
edn_genbits 173.920s 14579.981us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.470s 20.603us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.860s 176.206us 200 200 100.00
errs 100 100 100.00
edn_err 1.530s 20.353us 100 100 100.00
disable 92 100 92.00
edn_disable 1.300s 13.318us 50 50 100.00
edn_disable_auto_req_mode 4.370s 500.000us 42 50 84.00
stress_all 50 50 100.00
edn_stress_all 6.760s 388.342us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.320s 15.567us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.670s 59.203us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.660s 101.121us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.660s 101.121us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.280s 15.470us 5 5 100.00
edn_csr_rw 1.360s 24.214us 20 20 100.00
edn_csr_aliasing 1.980s 67.726us 5 5 100.00
edn_same_csr_outstanding 1.630s 71.733us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.280s 15.470us 5 5 100.00
edn_csr_rw 1.360s 24.214us 20 20 100.00
edn_csr_aliasing 1.980s 67.726us 5 5 100.00
edn_same_csr_outstanding 1.630s 71.733us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 4.830s 762.987us 20 20 100.00
edn_sec_cm 6.990s 563.836us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.130s 49.186us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.860s 176.206us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.990s 563.836us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.990s 563.836us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 6.990s 563.836us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 6.990s 563.836us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.860s 176.206us 200 200 100.00
edn_sec_cm 6.990s 563.836us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.860s 176.206us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 4.830s 762.987us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 42 50 84.00
edn_stress_all_with_rand_reset 112.300s 5862.723us 42 50 84.00

Error Messages

   Test seed line log context
Error-[FCIBH] Illegal bin hit
edn_stress_all_with_rand_reset 7446761899949227856477279120269579193221947949440236816199348766252112092656 285
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 2289985228 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup
edn_stress_all_with_rand_reset 111141377731527693212659302327772154953665070435995250520246084533373235297867 184
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1707944834 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 104882714482227820317387405077013264771037123294902516853832492923516323789640 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 106665988669935475353994647236580174139863948948492077704456383555777018102060 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 106723767699515367200129365803923669488950150219552065310891979160339232842993 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 19066644602269545803121260888680045539052797977360290526896295593310139415423 166
UVM_ERROR @ 280350867 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 280350867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 79246333596541061890129337072784328564534959559813609696554389692166223059256 144
UVM_ERROR @ 1110510703 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1110510703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 111939691399757942708557022292313152208270184187483148395407535418159823941954 204
UVM_ERROR @ 1355265250 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1355265250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 89339851153703757670683798247116200086692234222439924886081811246680313199177 407
UVM_ERROR @ 5862723391 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5862723391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 68109741801390691573278712917927880467981765988107544545297085930003678228765 131
UVM_ERROR @ 150409990 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 150409990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
edn_stress_all_with_rand_reset 41319399379544910026025351188681872645862257944034161280777670329040326594204 309
UVM_ERROR @ 3248703754 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3248703754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 335541376899832275685537090734682440711585936221345479958650196023159195463 88
UVM_FATAL @ 8441252 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x000a7612 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 8441252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 4841319934193151555556276654123245991825520540218460070596209149758603920903 88
UVM_FATAL @ 34118858 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x001ed902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 34118858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 41183652772661410294479473936193835890135312089099990469181531659268532592584 88
UVM_FATAL @ 30031068 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x000009c2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 30031068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 45640915695179567208682669604974450733133909107718899809808459445249431236237 88
UVM_FATAL @ 43797705 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x0057a972 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 43797705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 44312325639293853275601207024642038630153997057553447887690596210634239194590 88
UVM_FATAL @ 60492033 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00dd4602 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 60492033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---