Simulation Results: edn/edn1

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.11 %
  • code
  • 95.95 %
  • assert
  • 97.14 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.08 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
99.48%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.370s 18.058us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.260s 62.870us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.270s 14.481us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 7.300s 1003.896us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.820s 42.105us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.850s 45.333us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.270s 14.481us 20 20 100.00
edn_csr_aliasing 1.820s 42.105us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 65.340s 5624.288us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 65.340s 5624.288us 300 300 100.00
genbits 300 300 100.00
edn_genbits 65.340s 5624.288us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.540s 21.131us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.770s 202.350us 200 200 100.00
errs 100 100 100.00
edn_err 1.660s 30.625us 100 100 100.00
disable 95 100 95.00
edn_disable 1.280s 21.176us 50 50 100.00
edn_disable_auto_req_mode 8.930s 500.000us 45 50 90.00
stress_all 50 50 100.00
edn_stress_all 6.730s 334.118us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.230s 14.482us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.820s 143.854us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 5.050s 214.965us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 5.050s 214.965us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.260s 62.870us 5 5 100.00
edn_csr_rw 1.270s 14.481us 20 20 100.00
edn_csr_aliasing 1.820s 42.105us 5 5 100.00
edn_same_csr_outstanding 1.660s 31.079us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.260s 62.870us 5 5 100.00
edn_csr_rw 1.270s 14.481us 20 20 100.00
edn_csr_aliasing 1.820s 42.105us 5 5 100.00
edn_same_csr_outstanding 1.660s 31.079us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 5.420s 245.478us 20 20 100.00
edn_sec_cm 7.380s 492.148us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.390s 19.128us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.770s 202.350us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.380s 492.148us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.380s 492.148us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.380s 492.148us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.380s 492.148us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.770s 202.350us 200 200 100.00
edn_sec_cm 7.380s 492.148us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.770s 202.350us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 5.420s 245.478us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 45 50 90.00
edn_stress_all_with_rand_reset 91.470s 5601.716us 45 50 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 66629857792591003006403788314638222982947567704111098834374330428936446833916 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 58646528343763566849093823400187781124019223814897727673597887033008268265982 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 86903158548294220008760808249787668098547858898939889631374245592884828737525 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 35461509900156349981331560237402431824007322854855088364437588172607257422727 143
UVM_ERROR @ 120231091 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 120231091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 48694452154983196749891528437187974283819120914910934064378882147831783312300 216
UVM_ERROR @ 2568368249 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2568368249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 65865697354891108880399821015158317954052311504821729659180639122163583507692 260
UVM_ERROR @ 2108905327 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2108905327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 22186214382460391195169616104622936924488804775977557234711680770219097781968 281
UVM_ERROR @ 3136183018 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3136183018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 61248501832000309166828943425807213959256922567689943390690136670372827949715 268
UVM_ERROR @ 2434456106 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2434456106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 43102920828186306872947051430729059845019431505603542795677416113990342287272 88
UVM_FATAL @ 50432077 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000932 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 50432077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 60223724213327092566765222702686110692841000137252068281215797038095936770932 88
UVM_FATAL @ 17513324 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x002f7942 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 17513324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---