Simulation Results: keymgr

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.97 %
  • code
  • 99.02 %
  • assert
  • 97.72 %
  • func
  • 91.16 %
  • line
  • 99.20 %
  • branch
  • 99.09 %
  • cond
  • 98.16 %
  • toggle
  • 98.66 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.48%
V2S
99.74%
V3
54.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 12.950s 3037.547us 50 50 100.00
random 50 50 100.00
keymgr_random 73.550s 41305.284us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.570s 74.547us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.780s 50.816us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 16.010s 1295.516us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 10.470s 696.260us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.170s 462.835us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.780s 50.816us 20 20 100.00
keymgr_csr_aliasing 10.470s 696.260us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 76.820s 6530.115us 50 50 100.00
sideload 200 200 100.00
keymgr_sideload 22.300s 1664.493us 50 50 100.00
keymgr_sideload_kmac 32.160s 3298.280us 50 50 100.00
keymgr_sideload_aes 42.560s 3795.322us 50 50 100.00
keymgr_sideload_otbn 32.810s 1719.424us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 23.320s 1303.959us 50 50 100.00
lc_disable 49 50 98.00
keymgr_lc_disable 6.470s 3124.842us 49 50 98.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 9.230s 1128.972us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 52.410s 8392.553us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 35.380s 3963.419us 50 50 100.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 17.380s 2440.260us 50 50 100.00
stress_all 47 50 94.00
keymgr_stress_all 666.430s 50242.057us 47 50 94.00
intr_test 50 50 100.00
keymgr_intr_test 1.310s 41.934us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.360s 18.367us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 4.410s 197.037us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 4.410s 197.037us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.570s 74.547us 5 5 100.00
keymgr_csr_rw 1.780s 50.816us 20 20 100.00
keymgr_csr_aliasing 10.470s 696.260us 5 5 100.00
keymgr_same_csr_outstanding 4.410s 1249.369us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.570s 74.547us 5 5 100.00
keymgr_csr_rw 1.780s 50.816us 20 20 100.00
keymgr_csr_aliasing 10.470s 696.260us 5 5 100.00
keymgr_same_csr_outstanding 4.410s 1249.369us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 20.360s 15489.543us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_tl_intg_err 8.020s 831.441us 20 20 100.00
keymgr_sec_cm 20.360s 15489.543us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 4.890s 899.637us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 4.890s 899.637us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 4.890s 899.637us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 4.890s 899.637us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 15.400s 1240.825us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 20.360s 15489.543us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 20.360s 15489.543us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 8.020s 831.441us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 4.890s 899.637us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 76.820s 6530.115us 50 50 100.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_csr_rw 1.780s 50.816us 20 20 100.00
keymgr_random 73.550s 41305.284us 50 50 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_csr_rw 1.780s 50.816us 20 20 100.00
keymgr_random 73.550s 41305.284us 50 50 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_csr_rw 1.780s 50.816us 20 20 100.00
keymgr_random 73.550s 41305.284us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 49 50 98.00
keymgr_lc_disable 6.470s 3124.842us 49 50 98.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 35.380s 3963.419us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 35.380s 3963.419us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 73.550s 41305.284us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 22.410s 1370.791us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.360s 15489.543us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.360s 15489.543us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 20.360s 15489.543us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 43.020s 1828.037us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 49 50 98.00
keymgr_lc_disable 6.470s 3124.842us 49 50 98.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 20.360s 15489.543us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.360s 15489.543us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 20.360s 15489.543us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 43.020s 1828.037us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 43.020s 1828.037us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 20.360s 15489.543us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 43.020s 1828.037us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.360s 15489.543us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 43.020s 1828.037us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 27 50 54.00
keymgr_stress_all_with_rand_reset 17.440s 1131.304us 27 50 54.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 2828559580529998638722513921836082022600884380168221331678482445225576814955 687
UVM_ERROR @ 897350826 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 897350826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 25255788215567967869913741443636790728408906877378373463209685702969959159379 112
UVM_ERROR @ 605287374 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 605287374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 105235291587250573699678968824562970535049720477272589330793119831560849198637 1222
UVM_ERROR @ 1293821158 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1293821158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 32029666273893049187568196576576726400957424379486932153072637301002103804264 368
UVM_ERROR @ 791483781 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 791483781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 79733379221601412208470387305530096185149110462275187753261797745876001101187 192
UVM_ERROR @ 162965719 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 162965719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 34035193064070082438919277658530402838283163871953853478425103938258742608394 302
UVM_ERROR @ 241943277 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 241943277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 100022633431488723098498839877516799066391898875707064841934264956910794476483 782
UVM_ERROR @ 1402854843 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1402854843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 18459363628756229347184275731889694095081702258834405697671437337872744756998 242
UVM_ERROR @ 202246826 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 202246826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 53533182939987819261373677448468051828114853736274760805102994567601213523955 1019
UVM_ERROR @ 459239510 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 459239510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 61245692627681503130988394964484692535301573976350769835588865138706679588042 220
UVM_ERROR @ 626498460 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 626498460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 48255316482152232213401407948269267146580193794243336129820496113629806517418 509
UVM_ERROR @ 164977226 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 164977226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 16232565828425829170957659712534803477903557288348671413303696353101004699368 144
UVM_ERROR @ 228427870 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 228427870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 46406744278450851917934766570969600526470676164725152092837232789126079944655 163
UVM_ERROR @ 517231337 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 517231337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 919005767305208803260484211321214600655773691189784234144736138446832899155 552
UVM_ERROR @ 407437954 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 407437954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 13300843968770242645554134258385586422950629085903509799967875247135691345553 636
UVM_ERROR @ 332507870 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 332507870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 111620724600525956364105758213153347818695075796694353114116624625950594091673 256
UVM_ERROR @ 916217296 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 916217296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 45275293898918795949121087670891913926202155186103832303372154329969445654277 253
UVM_ERROR @ 867796057 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 867796057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 78572683560782664589467888649395636833191179396019705426861798047629562828097 179
UVM_ERROR @ 881908206 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 881908206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 7716572406743757791547740193107435185017227594061713384111898976279941104812 173
UVM_ERROR @ 227359126 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 227359126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 24660325251394842620812409486234858350562226414761410641277288007978178946666 586
UVM_ERROR @ 531570484 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 531570484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 1041671215673450332741198438788408979188368687067453679888470372960312325550 625
UVM_ERROR @ 950736629 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 950736629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 58919581799728345419751244333093630012770741487849737537815279776686241840443 1152
UVM_ERROR @ 520535663 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 520535663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 114402405821278714686166577848403907633051833307608532515272196819862733077233 612
UVM_ERROR @ 793246197 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 793246197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_stress_all 92207421666600463705231075100261795774455036197441009836088050503681955889664 131
UVM_ERROR @ 5275397 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 5275397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 56901164254537007033215392191739329272429516722937090990369433025796857449210 1645
UVM_ERROR @ 540654736 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 540654736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Attestation Aes
keymgr_lc_disable 88607788255170393851090159016298875779008348225789125256346395828330794795466 322
UVM_ERROR @ 134036653 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (5871019733847025646337092295919802842118368242867584736796168660890482027417004349128113643086783037664983630185837532999677537660101708858395686811221891 [0x7018f259b30eb1a0cc8eac4e4a91badf38383f1382eaec71fe14792ca4feb61c7becdc5e5d59bba4154ea8ce4fa3ace66bdf8ad6513e7eaa7dfa20e706cc3f83] vs 5871019733847025646337092295919802842118368242867584736796168660890482027417004349128113643086783037664983630185837532999677537660101708858395686811221891 [0x7018f259b30eb1a0cc8eac4e4a91badf38383f1382eaec71fe14792ca4feb61c7becdc5e5d59bba4154ea8ce4fa3ace66bdf8ad6513e7eaa7dfa20e706cc3f83]) AES key at state StDisabled for Attestation Aes
UVM_INFO @ 134036653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_*
keymgr_stress_all 95185028010664053426339057780818456967136916452087202659567858461733742339186 281
UVM_ERROR @ 334469249 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3341711553 [0xc72e78c1] vs 3341711553 [0xc72e78c1]) reg name: keymgr_reg_block.sw_share1_output_5
UVM_INFO @ 334469249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---