Simulation Results: sram_ctrl/main

 
20/04/2026 00:07:04 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.74 %
  • code
  • 96.96 %
  • assert
  • 96.46 %
  • func
  • 96.80 %
  • block
  • 96.35 %
  • line
  • 97.11 %
  • branch
  • 94.65 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 7.000s 673.712us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 14.062us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 23.256us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 3.000s 132.721us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 14.890us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 1404.962us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 23.256us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 14.890us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 335.000s 20687.266us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 158.000s 22226.877us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 78.000s 8849.699us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 339.000s 27744.939us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 227.000s 190120.089us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 127.000s 113521.154us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 83.000s 54334.333us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 73.000s 30690.392us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 8.000s 2729.890us 5 5 100.00
sram_ctrl_partial_access_b2b 419.000s 19770.326us 5 5 100.00
max_throughput 5 15 33.33
sram_ctrl_max_throughput 7.000s 7297.921us 0 5 0.00
sram_ctrl_throughput_w_partial_write 8.000s 2765.763us 5 5 100.00
sram_ctrl_throughput_w_readback 7.000s 2736.255us 0 5 0.00
regwen 5 5 100.00
sram_ctrl_regwen 20.000s 17151.949us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 4.000s 1346.118us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 537.000s 147707.254us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 28.726us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 146.205us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 146.205us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 14.062us 5 5 100.00
sram_ctrl_csr_rw 2.000s 23.256us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 14.890us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 29.648us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 14.062us 5 5 100.00
sram_ctrl_csr_rw 2.000s 23.256us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 14.890us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 29.648us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 48.000s 7373.271us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 1421.123us 20 20 100.00
sram_ctrl_sec_cm 5.000s 737.225us 5 5 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 737.225us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 1421.123us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 20.000s 17151.949us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 20.000s 17151.949us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 23.256us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 73.000s 30690.392us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 73.000s 30690.392us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 73.000s 30690.392us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 83.000s 54334.333us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 7.000s 715.417us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 48.000s 7373.271us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 8.000s 5114.577us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 7.000s 673.712us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 7.000s 673.712us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 73.000s 30690.392us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 737.225us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 83.000s 54334.333us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 737.225us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 737.225us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 7.000s 673.712us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 737.225us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 73.000s 2643.818us 5 5 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 105005150193796429690978782847617363512236841350781585958219682461781742576455 102
UVM_FATAL @ 717173685 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 717173685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 21228370336530540203369369444360098932724516631241931201801477230028785400438 102
UVM_FATAL @ 1317421822 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 1317421822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 109598389458166188662360614730297290263113062326735041880132563911607906588740 102
UVM_FATAL @ 688692083 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 688692083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 30851667500732752320071681753600952879049360098025992606882084485160343204528 102
UVM_FATAL @ 2632139567 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 2632139567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 21389210707094300944857164525432245281369079970477542227107112622271161428765 102
UVM_FATAL @ 657852145 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 657852145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 81478963331419243173208550000978068847999925856983917194307790675009746493526 102
UVM_FATAL @ 2736255178 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 2736255178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 100511388573114600114476600291208612513161092233344164106960406588777491924809 102
UVM_FATAL @ 7297921270 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 7297921270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 46798465873708515725801750561412631971399887526928201539357369171832561902174 102
UVM_FATAL @ 1688299466 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 1688299466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 48495228816950217034321631195649133809185462856889210912634454280228861703952 102
UVM_FATAL @ 1328320547 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 1328320547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 98062495978990975021767527148001116806057734026893161899232225032584588121516 102
UVM_FATAL @ 1342106015 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 1342106015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---