Simulation Results: alert_handler

 
24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.01 %
  • code
  • 98.97 %
  • assert
  • 98.92 %
  • func
  • 99.14 %
  • line
  • 99.99 %
  • branch
  • 99.99 %
  • cond
  • 97.50 %
  • toggle
  • 97.37 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.07%
V2S
98.87%
V3
74.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
alert_handler_smoke 77.640s 4867.933us 50 50 100.00
csr_hw_reset 5 5 100.00
alert_handler_csr_hw_reset 7.090s 43.925us 5 5 100.00
csr_rw 20 20 100.00
alert_handler_csr_rw 11.390s 555.721us 20 20 100.00
csr_bit_bash 5 5 100.00
alert_handler_csr_bit_bash 391.810s 8377.497us 5 5 100.00
csr_aliasing 5 5 100.00
alert_handler_csr_aliasing 298.830s 3725.610us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
alert_handler_csr_mem_rw_with_rand_reset 12.130s 133.121us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
alert_handler_csr_rw 11.390s 555.721us 20 20 100.00
alert_handler_csr_aliasing 298.830s 3725.610us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 50 50 100.00
alert_handler_esc_alert_accum 361.460s 11036.387us 50 50 100.00
esc_timeout 50 50 100.00
alert_handler_esc_intr_timeout 64.870s 804.573us 50 50 100.00
entropy 49 50 98.00
alert_handler_entropy 3384.440s 213050.641us 49 50 98.00
sig_int_fail 50 50 100.00
alert_handler_sig_int_fail 82.600s 4438.154us 50 50 100.00
clk_skew 50 50 100.00
alert_handler_smoke 77.640s 4867.933us 50 50 100.00
random_alerts 50 50 100.00
alert_handler_random_alerts 90.330s 11715.208us 50 50 100.00
random_classes 50 50 100.00
alert_handler_random_classes 87.480s 1138.936us 50 50 100.00
ping_timeout 19 50 38.00
alert_handler_ping_timeout 664.760s 16499.882us 19 50 38.00
lpg 98 100 98.00
alert_handler_lpg 2878.420s 640827.448us 48 50 96.00
alert_handler_lpg_stub_clk 3041.520s 342152.301us 50 50 100.00
stress_all 49 50 98.00
alert_handler_stress_all 4085.430s 296438.098us 49 50 98.00
alert_handler_entropy_stress_test 20 20 100.00
alert_handler_entropy_stress 150.470s 10055.581us 20 20 100.00
alert_handler_alert_accum_saturation 20 20 100.00
alert_handler_alert_accum_saturation 5.830s 57.729us 20 20 100.00
intr_test 50 50 100.00
alert_handler_intr_test 2.780s 22.790us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
alert_handler_tl_errors 27.910s 1273.747us 20 20 100.00
tl_d_illegal_access 20 20 100.00
alert_handler_tl_errors 27.910s 1273.747us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
alert_handler_csr_hw_reset 7.090s 43.925us 5 5 100.00
alert_handler_csr_rw 11.390s 555.721us 20 20 100.00
alert_handler_csr_aliasing 298.830s 3725.610us 5 5 100.00
alert_handler_same_csr_outstanding 54.650s 3005.828us 20 20 100.00
tl_d_partial_access 50 50 100.00
alert_handler_csr_hw_reset 7.090s 43.925us 5 5 100.00
alert_handler_csr_rw 11.390s 555.721us 20 20 100.00
alert_handler_csr_aliasing 298.830s 3725.610us 5 5 100.00
alert_handler_same_csr_outstanding 54.650s 3005.828us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
alert_handler_shadow_reg_errors 373.770s 9866.332us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
alert_handler_shadow_reg_errors 373.770s 9866.332us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
alert_handler_shadow_reg_errors 373.770s 9866.332us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
alert_handler_shadow_reg_errors 373.770s 9866.332us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
alert_handler_shadow_reg_errors_with_csr_rw 1288.320s 37455.618us 20 20 100.00
tl_intg_err 25 25 100.00
alert_handler_tl_intg_err 79.640s 4195.907us 20 20 100.00
alert_handler_sec_cm 83.520s 5785.647us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
alert_handler_tl_intg_err 79.640s 4195.907us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
alert_handler_shadow_reg_errors 373.770s 9866.332us 20 20 100.00
sec_cm_ping_timer_config_regwen 50 50 100.00
alert_handler_smoke 77.640s 4867.933us 50 50 100.00
sec_cm_alert_config_regwen 50 50 100.00
alert_handler_smoke 77.640s 4867.933us 50 50 100.00
sec_cm_alert_loc_config_regwen 50 50 100.00
alert_handler_smoke 77.640s 4867.933us 50 50 100.00
sec_cm_class_config_regwen 50 50 100.00
alert_handler_smoke 77.640s 4867.933us 50 50 100.00
sec_cm_alert_intersig_diff 50 50 100.00
alert_handler_sig_int_fail 82.600s 4438.154us 50 50 100.00
sec_cm_lpg_intersig_mubi 48 50 96.00
alert_handler_lpg 2878.420s 640827.448us 48 50 96.00
sec_cm_esc_intersig_diff 50 50 100.00
alert_handler_sig_int_fail 82.600s 4438.154us 50 50 100.00
sec_cm_alert_rx_intersig_bkgn_chk 49 50 98.00
alert_handler_entropy 3384.440s 213050.641us 49 50 98.00
sec_cm_esc_tx_intersig_bkgn_chk 49 50 98.00
alert_handler_entropy 3384.440s 213050.641us 49 50 98.00
sec_cm_esc_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 83.520s 5785.647us 5 5 100.00
sec_cm_ping_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 83.520s 5785.647us 5 5 100.00
sec_cm_esc_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 83.520s 5785.647us 5 5 100.00
sec_cm_ping_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 83.520s 5785.647us 5 5 100.00
sec_cm_esc_timer_fsm_global_esc 5 5 100.00
alert_handler_sec_cm 83.520s 5785.647us 5 5 100.00
sec_cm_accu_ctr_redun 5 5 100.00
alert_handler_sec_cm 83.520s 5785.647us 5 5 100.00
sec_cm_esc_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 83.520s 5785.647us 5 5 100.00
sec_cm_ping_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 83.520s 5785.647us 5 5 100.00
sec_cm_ping_timer_lfsr_redun 5 5 100.00
alert_handler_sec_cm 83.520s 5785.647us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 37 50 74.00
alert_handler_stress_all_with_rand_reset 645.190s 22913.158us 37 50 74.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 27518083803740519334719955585324755319714596021902421523996020710730015400056 84
UVM_ERROR @ 108959607 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 108959607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 94112507233109743186662216239180927245553841924540581478934937324369309381840 118
UVM_ERROR @ 811761805 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 811761805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 37772336787601576042801074717755334577918833877366170343647388863392272905933 84
UVM_ERROR @ 757459462 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 757459462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 38102895738997285160012092235284424902199248455144297489548305967535752908087 85
UVM_ERROR @ 211819215 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 211819215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 42307448732896209805225783903309933831229307468141765525402518892060698005834 144
UVM_ERROR @ 4819559875 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4819559875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 44642793225092773797211463492964904266604324435924724813392095794739270442466 84
UVM_ERROR @ 217219626 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 217219626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 101102758649174460111731231800127912288090258741841293285532094729215034801611 83
UVM_ERROR @ 115160799 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 115160799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 28990680982176637617314344554126882035552205881109539995199864861256800867681 83
UVM_ERROR @ 430743781 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 430743781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 64248895556539915553819620629520717965929364158773608845696192906995772313566 121
UVM_ERROR @ 4871615902 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4871615902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 94082511732178294477090933332584098315866806337150832469871737326233400278249 84
UVM_ERROR @ 2342940335 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2342940335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 38003186701676416707210895761909332712616437173459481331185709663548271535206 83
UVM_ERROR @ 2732464279 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2732464279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model.
alert_handler_ping_timeout 76518366072973743082962645311916636407711907898205560596171977043083308814071 80
UVM_ERROR @ 650046628 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 650046628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 138010800364498495007308733188014908434584406371208714578771302356366835244 80
UVM_ERROR @ 318618014 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 318618014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_lpg 94513585046507334341654560198667241775811490755129592024895550387905928963611 80
UVM_ERROR @ 489498858 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 489498858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 49749455068717393855376395420652470659272436667810619492686162628598198937635 80
UVM_ERROR @ 262926353 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 262926353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 9788585066317039210006372312401252645661867206880491660762618531725303043020 80
UVM_ERROR @ 658293025 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 658293025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 7874669433590081309833706565134151625056727827252584546349697705465353061530 153
UVM_ERROR @ 15406716701 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 15406716701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 113470014760215382262710115840901498721674890313464626221436926195329346959246 135
UVM_ERROR @ 9148727408 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 9148727408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 108142059884271658781519280079848138794225548201028191914727012198885074081172 87
UVM_ERROR @ 4228745664 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 4228745664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 113987997505464629647356643034703497161501306266572900915352946136817851376164 96
UVM_ERROR @ 5966040749 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 5966040749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 106134937973677711018456588652166848371016653810628093069079236128625792430537 102
UVM_ERROR @ 14485963322 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 14485963322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 57723754765613217856204467557066158643476402404161543949107708829911460578297 147
UVM_ERROR @ 9390676548 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 9390676548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 228653712501165729806565265975246488566647092474433853078159159585634254989 102
UVM_ERROR @ 19876302530 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 19876302530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 110053592377401539237871443622840044554924839692816098302941643950230631969990 111
UVM_ERROR @ 20862709195 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 20862709195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 35256806258907692196381263653655247384199680556260140989695512277600329989615 120
UVM_ERROR @ 49181072647 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 49181072647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 81773230345533247437613901307799585066308567043498206664080029414841199771075 111
UVM_ERROR @ 18593227170 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 18593227170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 23345511474350489781108094031278259607270666771230089417628948626185174819453 126
UVM_ERROR @ 12773883628 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 12773883628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 33662668894551501312842052701894296787196913106159409856293667333255005752548 118
UVM_ERROR @ 8324987461 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 8324987461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 51404871021933436425955914664339770693174944993464510959349697658406786575440 105
UVM_ERROR @ 18276199288 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 18276199288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 46594976362462614340929966032748292896791323124663584462106298905256110477172 141
UVM_ERROR @ 10066467894 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 10066467894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 20812779933318746843557628776953963365518905398796511685577725539601679167812 93
UVM_ERROR @ 4976631360 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 4976631360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 75156738276061934428345090102927395887222479222018911533565713184996643369307 90
UVM_ERROR @ 6132096715 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 6132096715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 58829660405816967307164300630032102686130346433059728195443057820993939047910 113
UVM_ERROR @ 15584125837 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 15584125837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 51477421989867331643087427012868093770775335725719475917671821716625137777027 84
UVM_ERROR @ 10876941853 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 10876941853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 101917105448032293408949578540563686850935519858477490986701646319268130773034 87
UVM_ERROR @ 4804959011 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 4804959011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 2066148722639151641321885968821757820711845334599629687518287037719029740132 99
UVM_ERROR @ 7942188489 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 7942188489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 83626682106719006612582494482566128415731994577562153711086510586473881289663 113
UVM_ERROR @ 16648133774 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 16648133774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 34891116879438552813400597796974424040648479976355303693127593322369936975471 114
UVM_ERROR @ 9853125837 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 9853125837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 79557178161952307849577036443486970744648183805653686592581459234162336394328 84
UVM_ERROR @ 964171914 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 964171914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 66546852493457308062619942924133689457810365064177828896735980156035561943541 93
UVM_ERROR @ 18534776713 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 18534776713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 8111851973930742884775126540726624993455017241064720785456074785013190521240 114
UVM_ERROR @ 26391471903 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 26391471903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 87220875264729838329552809345059515793123943968853187846755204971307060427651 96
UVM_ERROR @ 3844945879 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 3844945879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 97889245729222035928276313557316686509669340672193474162277501505145443796887 117
UVM_ERROR @ 11672841050 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 11672841050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail)
alert_handler_stress_all 8326280675070913778772056749752047581553610494700505346723191253464644694031 172
UVM_ERROR @ 4852808454 ps: (alert_handler_scoreboard.sv:258) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[2]: saw 0, but expected 1. (is_int_err = 1, local_alert_type = LocalEscIntFail)
UVM_INFO @ 4852808454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_accum_cnt
alert_handler_lpg 105918362702247839608750838513008017197215931028456273661329835211306633539101 82
UVM_ERROR @ 30063022163 ps: (alert_handler_scoreboard.sv:490) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (860 [0x35c] vs 861 [0x35d]) reg name: alert_handler_reg_block.classc_accum_cnt
UVM_INFO @ 30063022163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
alert_handler_stress_all_with_rand_reset 108073355643845226824786035391775714716040325107194713090703610634122539227133 82
UVM_ERROR @ 205596376 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 205596376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 54186010225240033401778450785704983340371804245134880540659314293910630550389 119
UVM_ERROR @ 5722089283 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5722089283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
alert_handler_entropy 73312309159910464661084976590852060267163781208918679477116638998988935539066 None
Job timed out after 60 minutes