Simulation Results: dma

 
24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.83 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 78.33 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 34.000s 309.610us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 33.000s 229.050us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 33.000s 604.436us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 2.000s 52.255us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 2.000s 95.178us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 13.000s 8089.893us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 8.000s 550.003us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 129.728us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 2.000s 95.178us 20 20 100.00
dma_csr_aliasing 8.000s 550.003us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 141.000s 34445.002us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 1513.000s 375815.022us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 698.000s 200307.335us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 698.000s 200307.335us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 1513.000s 375815.022us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 1092.000s 101261.723us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 698.000s 200307.335us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 44.000s 8464.854us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 218.000s 17128.321us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 15.000s 28.690us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 2.000s 91.298us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 4.000s 505.139us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 4.000s 505.139us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 2.000s 52.255us 5 5 100.00
dma_csr_rw 2.000s 95.178us 20 20 100.00
dma_csr_aliasing 8.000s 550.003us 5 5 100.00
dma_same_csr_outstanding 3.000s 120.916us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 2.000s 52.255us 5 5 100.00
dma_csr_rw 2.000s 95.178us 20 20 100.00
dma_csr_aliasing 8.000s 550.003us 5 5 100.00
dma_same_csr_outstanding 3.000s 120.916us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 42.000s 961.552us 5 5 100.00
dma_generic_stress 1092.000s 101261.723us 5 5 100.00
dma_handshake_stress 698.000s 200307.335us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 32.000s 313.524us 15 15 100.00
tl_intg_err 25 25 100.00
dma_sec_cm 15.000s 19.907us 5 5 100.00
dma_tl_intg_err 5.000s 355.596us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 184.000s 11509.886us 25 25 100.00
dma_longer_transfer 38.000s 7207.573us 5 5 100.00
dma_stress_all_with_rand_reset 28.000s 1994.063us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 70906798153611918038696582996199013413075127707253731217994668106193169782273 102
UVM_ERROR @ 1994063099ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1994063099ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---