Simulation Results: edn/edn0

 
24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.30 %
  • code
  • 95.64 %
  • assert
  • 97.61 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.20 %
  • toggle
  • 97.17 %
  • FSM
  • 91.40 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.380s 17.214us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.380s 16.790us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.190s 16.729us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.790s 344.835us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.840s 44.176us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.860s 273.385us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.190s 16.729us 20 20 100.00
edn_csr_aliasing 1.840s 44.176us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 77.520s 8748.283us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 77.520s 8748.283us 300 300 100.00
genbits 300 300 100.00
edn_genbits 77.520s 8748.283us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.460s 21.936us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.830s 35.110us 200 200 100.00
errs 100 100 100.00
edn_err 1.680s 27.396us 100 100 100.00
disable 92 100 92.00
edn_disable 1.350s 15.274us 50 50 100.00
edn_disable_auto_req_mode 5.140s 500.000us 42 50 84.00
stress_all 50 50 100.00
edn_stress_all 7.160s 446.090us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.440s 24.879us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.600s 34.330us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.640s 460.906us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.640s 460.906us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.380s 16.790us 5 5 100.00
edn_csr_rw 1.190s 16.729us 20 20 100.00
edn_csr_aliasing 1.840s 44.176us 5 5 100.00
edn_same_csr_outstanding 1.580s 148.069us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.380s 16.790us 5 5 100.00
edn_csr_rw 1.190s 16.729us 20 20 100.00
edn_csr_aliasing 1.840s 44.176us 5 5 100.00
edn_same_csr_outstanding 1.580s 148.069us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 3.050s 209.833us 20 20 100.00
edn_sec_cm 6.930s 1582.169us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.390s 23.208us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.830s 35.110us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.930s 1582.169us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.930s 1582.169us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 6.930s 1582.169us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 6.930s 1582.169us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.830s 35.110us 200 200 100.00
edn_sec_cm 6.930s 1582.169us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.830s 35.110us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 3.050s 209.833us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 40 50 80.00
edn_stress_all_with_rand_reset 122.130s 50642.371us 40 50 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 20898445304150793447808386548609299589703284634008112454412009456627246069252 234
UVM_ERROR @ 1803201626 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1803201626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 2602679576450136225035344367884215783056531797357324463225953964121075103618 132
UVM_ERROR @ 786756698 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 786756698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 93298612767226473354167381892212364510014966096113090830159498293802514306468 125
UVM_ERROR @ 113252402 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 113252402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 6483888861767824038592600396964215402202027821794810584532287625147320621533 185
UVM_ERROR @ 1312134808 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1312134808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 60717010448884248337305144068778277891771977229120161879163655789564333664542 231
UVM_ERROR @ 235882034 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 235882034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 64255274107976743744764440553353652046192646613134722944528696640348995874846 332
UVM_ERROR @ 4502235829 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4502235829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 113544484855765717043488532102197283071683357796477740962269585015686605739762 253
UVM_ERROR @ 2073640134 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2073640134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 1095990899116772140332977007744280821402328748427216605403930761740236044885 209
UVM_ERROR @ 2188919361 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2188919361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 43340987360167637880691290534297366493960648574789049393002901838666755521111 192
UVM_ERROR @ 1249666067 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1249666067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 91089613750754457030140488333725584543852189390801008866694625777419268098524 237
UVM_ERROR @ 2867090569 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2867090569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 17063611492133392553400327752972711794309500382547909248414018316669671105162 88
UVM_FATAL @ 77894838 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x003019a2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 77894838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 87187240959877120160470271311265754252587855752619820323447092622333635789631 88
UVM_FATAL @ 39099012 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00001903 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 39099012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 55967285140359557222995276640015138832898307405952727938513084650386036728349 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 86458250712523596504750760212390513975014299038439847419465062375252492239186 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 91017226432553262813669964000249807492290552501535012137987518272214853519355 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 71661615612863336037799462854004213729156852357096426878661071396929021729266 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 97969361084011364272528754176499427311357178537120420427486336845610071240834 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 55705959344394551138371023343172852036377558221618454676411415131223015670904 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---