Simulation Results: edn/edn1

 
24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.10 %
  • code
  • 95.71 %
  • assert
  • 97.14 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.15 %
  • FSM
  • 94.32 %
Validation stages
V1
100.00%
V2
99.28%
V2S
100.00%
V3
92.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.270s 17.079us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.820s 37.923us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.820s 18.663us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.310s 668.607us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.050s 27.041us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.480s 64.410us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.820s 18.663us 20 20 100.00
edn_csr_aliasing 1.050s 27.041us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 4.010s 450.912us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 4.010s 450.912us 300 300 100.00
genbits 300 300 100.00
edn_genbits 4.010s 450.912us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.360s 24.526us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.530s 44.798us 200 200 100.00
errs 100 100 100.00
edn_err 1.500s 29.012us 100 100 100.00
disable 93 100 93.00
edn_disable 1.190s 35.681us 50 50 100.00
edn_disable_auto_req_mode 16.650s 500.000us 43 50 86.00
stress_all 50 50 100.00
edn_stress_all 5.310s 401.880us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.870s 17.712us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 2.920s 420.513us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.880s 275.882us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.880s 275.882us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.820s 37.923us 5 5 100.00
edn_csr_rw 0.820s 18.663us 20 20 100.00
edn_csr_aliasing 1.050s 27.041us 5 5 100.00
edn_same_csr_outstanding 1.120s 41.663us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.820s 37.923us 5 5 100.00
edn_csr_rw 0.820s 18.663us 20 20 100.00
edn_csr_aliasing 1.050s 27.041us 5 5 100.00
edn_same_csr_outstanding 1.120s 41.663us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 2.050s 1385.121us 20 20 100.00
edn_sec_cm 5.360s 395.880us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.230s 29.224us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.530s 44.798us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.360s 395.880us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.360s 395.880us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 5.360s 395.880us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 5.360s 395.880us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.530s 44.798us 200 200 100.00
edn_sec_cm 5.360s 395.880us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.530s 44.798us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.050s 1385.121us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 46 50 92.00
edn_stress_all_with_rand_reset 88.560s 49299.680us 46 50 92.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 93294439877521694046583416823618731401475355039947047861281025241353395171505 222
UVM_ERROR @ 2061960259 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2061960259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 3626027525328950465798392795269826992033360726211584851228745359417975716236 151
UVM_ERROR @ 547941335 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 547941335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 114564877822749079493470096195931358171823294018951184185988898598650609851375 201
UVM_ERROR @ 2348347460 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2348347460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 46847529570674450606574639183923116632991202213920350517584315686820950955658 209
UVM_ERROR @ 1703434335 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1703434335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 75766288584646985083534550169445767925403723580063712540171466328358311410791 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 34784878740832639976100362227335782695651303065103052592548985211187711822294 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 105571386844917377828180734000039467720246070677188993489156568810168161659101 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 102054328338666870973111131047697064055359328484022321758323813628818778018703 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 67141496134702730713232660353399869630539509926186469158241769382173104469226 88
UVM_FATAL @ 10522762 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00935902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 10522762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 107137857988846827597525898981523795828006055679349027604592903898599152093581 88
UVM_FATAL @ 12618956 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00f389a2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 12618956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit
edn_disable_auto_req_mode 88316089735987803067347254921435368641281149829717064631466850781487552553802 90
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 180791516 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup