Simulation Results: lc_ctrl/volatile_unlock_enabled

 
24/04/2026 16:00:28 DVSim: v1.17.3 sha: 8007f61 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.80 %
  • code
  • 89.05 %
  • assert
  • 96.13 %
  • func
  • 96.22 %
  • line
  • 97.87 %
  • branch
  • 97.06 %
  • cond
  • 82.59 %
  • toggle
  • 91.35 %
  • FSM
  • 76.36 %
Validation stages
V1
100.00%
V2
99.86%
V2S
100.00%
V3
34.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 6.720s 154.129us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.340s 20.409us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.400s 17.047us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.330s 812.217us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.590s 64.955us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.820s 107.992us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.400s 17.047us 20 20 100.00
lc_ctrl_csr_aliasing 1.590s 64.955us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 9.150s 245.042us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 17.350s 792.931us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.240s 17.018us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 5.030s 115.589us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 12.750s 267.415us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 13.670s 492.426us 50 50 100.00
security_escalation 260 260 100.00
lc_ctrl_state_failure 12.750s 267.415us 50 50 100.00
lc_ctrl_prog_failure 5.030s 115.589us 50 50 100.00
lc_ctrl_errors 13.670s 492.426us 50 50 100.00
lc_ctrl_security_escalation 10.860s 764.473us 50 50 100.00
lc_ctrl_jtag_state_failure 87.940s 15467.708us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.120s 5699.115us 20 20 100.00
lc_ctrl_jtag_errors 51.430s 32884.267us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 9.580s 1859.940us 20 20 100.00
lc_ctrl_jtag_state_post_trans 24.120s 5583.243us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.120s 5699.115us 20 20 100.00
lc_ctrl_jtag_errors 51.430s 32884.267us 20 20 100.00
lc_ctrl_jtag_access 17.020s 3352.877us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 30.010s 5154.398us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 5.340s 599.513us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.680s 444.048us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 46.800s 3432.565us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 12.600s 788.129us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.580s 139.899us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.180s 1201.470us 10 10 100.00
lc_ctrl_jtag_alert_test 2.380s 166.356us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 96.990s 12045.775us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.580s 17.476us 50 50 100.00
stress_all 49 50 98.00
lc_ctrl_stress_all 362.790s 66331.815us 49 50 98.00
alert_test 50 50 100.00
lc_ctrl_alert_test 2.090s 113.604us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 3.570s 707.807us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 3.570s 707.807us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.340s 20.409us 5 5 100.00
lc_ctrl_csr_rw 1.400s 17.047us 20 20 100.00
lc_ctrl_csr_aliasing 1.590s 64.955us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.810s 40.671us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.340s 20.409us 5 5 100.00
lc_ctrl_csr_rw 1.400s 17.047us 20 20 100.00
lc_ctrl_csr_aliasing 1.590s 64.955us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.810s 40.671us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 9.380s 1766.013us 5 5 100.00
lc_ctrl_tl_intg_err 4.280s 3049.035us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 4.280s 3049.035us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 17.350s 792.931us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 12.750s 267.415us 50 50 100.00
lc_ctrl_sec_cm 9.380s 1766.013us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 12.750s 267.415us 50 50 100.00
lc_ctrl_sec_cm 9.380s 1766.013us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 12.750s 267.415us 50 50 100.00
lc_ctrl_sec_cm 9.380s 1766.013us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 12.750s 267.415us 50 50 100.00
lc_ctrl_sec_cm 9.380s 1766.013us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 12.750s 267.415us 50 50 100.00
lc_ctrl_sec_cm 9.380s 1766.013us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 12.750s 267.415us 50 50 100.00
lc_ctrl_sec_cm 9.380s 1766.013us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 12.750s 267.415us 50 50 100.00
lc_ctrl_sec_cm 9.380s 1766.013us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 12.750s 267.415us 50 50 100.00
lc_ctrl_sec_cm 9.380s 1766.013us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 10.860s 764.473us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 9.150s 245.042us 50 50 100.00
lc_ctrl_jtag_state_post_trans 24.120s 5583.243us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 16.730s 2788.299us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 16.730s 2788.299us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 14.290s 894.841us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 15.260s 731.218us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 15.260s 731.218us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 17 50 34.00
lc_ctrl_stress_all_with_rand_reset 116.100s 5294.163us 17 50 34.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 87150689919386868825137428974427549116692949674212806424832646245364357881379 2037
UVM_ERROR @ 6797016288 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6797016288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96947793177328825567691051760451073301541211936331648907843289869650762319739 3469
UVM_ERROR @ 5066146555 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5066146555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 9253354916141288832875591896385914333949477567816856359005855942976015337732 1388
UVM_ERROR @ 2084745545 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2084745545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 32061783906340089690700220563326852248416688362226458120752588586608080741857 1633
UVM_ERROR @ 1645319168 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1645319168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 76683625927476496303267020333590829160347226262753135465643696130930382861967 5078
UVM_ERROR @ 3503456166 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3503456166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 3507944399535784218740388638341068460969431466606328122017434450923346310811 3558
UVM_ERROR @ 1856794094 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1856794094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 1136547840815077492361712738577585071749021670036646000630218260776481049509 3804
UVM_ERROR @ 5726701728 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5726701728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 34119046675474830546957846902342566545773095242356231841409222559428978631639 9518
UVM_ERROR @ 2731589988 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2731589988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 69508678506797275494671727072631725580559748546037816728422901603629402210746 7114
UVM_ERROR @ 9364708816 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9364708816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65079934619985207276379296023208497689176299463007596433105949373845132350726 249
UVM_ERROR @ 640905709 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 640905709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 109806902757669346051619530379332901059711064267255905644218765476846245205694 1277
UVM_ERROR @ 2909610073 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2909610073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 80212085156673412374830488293288222716576813915997107255740778169501877962822 6141
UVM_ERROR @ 2193235522 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2193235522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 30005207629512364507001630950534510758714285704674080248097965717320395193166 6643
UVM_ERROR @ 5294163487 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5294163487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14496107635887490412528213297713449758804236877207954561136713122167998209855 6667
UVM_ERROR @ 2833156957 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2833156957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 84475992044853559285404652076312315175985005089537687755465017629448338763309 163
UVM_ERROR @ 1982114445 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1982114445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 93115480969675512635567997184684143870592899825285272258811122139998096582318 4045
UVM_ERROR @ 3334422362 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3334422362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 63798757397352086207096120036937844646984936366413433928529389108136220514838 633
UVM_ERROR @ 11039668169 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11039668169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 24979769637277582754089610934668804118928128151172879223382749203979431365103 3532
UVM_ERROR @ 7390310792 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7390310792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 40299417306587513965720256991156616240473210029515593527347886490918686838246 4030
UVM_ERROR @ 2953082078 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2953082078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 112780147869843049022566957706532790885791076410698205594407669257115741297312 433
UVM_ERROR @ 2287854353 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2287854353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 7037363631976278099096228149308200770417511586227581669771293072410951210793 699
UVM_ERROR @ 1307990860 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1307990860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 69426686345956124209305324152366581050936216253920350215183438885970907554876 5160
UVM_ERROR @ 5283777406 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5283777406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 26689730448423124763015435557720142910272815616393151683572386969146590457983 4246
UVM_ERROR @ 2955446423 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2955446423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 50314038054300704256032248809932250635510909682201734181346916752099564534296 591
UVM_ERROR @ 1167383183 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1167383183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 76728804296589124727643367838932615776599721783665240811083595978232541950521 803
UVM_ERROR @ 2072769121 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2072769121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 88265557541194015432804238193006571372192004184569719423709389053819230047400 1064
UVM_ERROR @ 1773807885 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1773807885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 103875813674018377556704890430635132097498139515275348361596784404828150372395 209
UVM_ERROR @ 3066236502 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3066236502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 112252216252527993189306344326928820955907534361755390851499141036177742702061 705
UVM_ERROR @ 21313448408 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 21313448408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98384639644772068388486262693912119546901659942128520556758071516688633402283 11799
UVM_ERROR @ 6705349799 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6705349799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 56676942940320252940225540224418847100368697217497387701693103190938963995325 3233
UVM_ERROR @ 1373607657 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1373607657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 101799758836386130377003341945670429116103561594840048902016906940142728576807 150
UVM_ERROR @ 117281168 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 117281168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 36682188118951224507995199673237527115320657702153066101533024460625456051461 2144
UVM_ERROR @ 5768911848 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5768911848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:*
lc_ctrl_stress_all 15574453893204892490309366081475616190210809962004572972869309396058006503986 3196
UVM_ERROR @ 6503729437 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
UVM_INFO @ 6503729437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 38727388786155841726478078199403906117267185701433299975391237651276766164093 5778
UVM_ERROR @ 10331169513 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 10331169513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---