Simulation Results: alert_handler

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.04 %
  • code
  • 98.84 %
  • assert
  • 98.92 %
  • func
  • 99.36 %
  • line
  • 99.99 %
  • branch
  • 99.99 %
  • cond
  • 97.54 %
  • toggle
  • 96.69 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.07%
V2S
98.87%
V3
52.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
alert_handler_smoke 63.030s 3292.496us 50 50 100.00
csr_hw_reset 5 5 100.00
alert_handler_csr_hw_reset 12.910s 118.287us 5 5 100.00
csr_rw 20 20 100.00
alert_handler_csr_rw 13.270s 579.567us 20 20 100.00
csr_bit_bash 5 5 100.00
alert_handler_csr_bit_bash 541.470s 9778.202us 5 5 100.00
csr_aliasing 5 5 100.00
alert_handler_csr_aliasing 338.950s 30270.710us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
alert_handler_csr_mem_rw_with_rand_reset 18.670s 807.785us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
alert_handler_csr_rw 13.270s 579.567us 20 20 100.00
alert_handler_csr_aliasing 338.950s 30270.710us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 50 50 100.00
alert_handler_esc_alert_accum 387.850s 30812.333us 50 50 100.00
esc_timeout 50 50 100.00
alert_handler_esc_intr_timeout 74.470s 4297.404us 50 50 100.00
entropy 49 50 98.00
alert_handler_entropy 3269.280s 59129.444us 49 50 98.00
sig_int_fail 50 50 100.00
alert_handler_sig_int_fail 67.340s 1907.445us 50 50 100.00
clk_skew 50 50 100.00
alert_handler_smoke 63.030s 3292.496us 50 50 100.00
random_alerts 50 50 100.00
alert_handler_random_alerts 92.390s 5962.162us 50 50 100.00
random_classes 50 50 100.00
alert_handler_random_classes 108.460s 1437.526us 50 50 100.00
ping_timeout 19 50 38.00
alert_handler_ping_timeout 642.920s 91279.348us 19 50 38.00
lpg 98 100 98.00
alert_handler_lpg 3505.230s 259416.692us 48 50 96.00
alert_handler_lpg_stub_clk 2722.090s 203051.980us 50 50 100.00
stress_all 49 50 98.00
alert_handler_stress_all 3113.870s 67019.886us 49 50 98.00
alert_handler_entropy_stress_test 20 20 100.00
alert_handler_entropy_stress 89.660s 4022.062us 20 20 100.00
alert_handler_alert_accum_saturation 20 20 100.00
alert_handler_alert_accum_saturation 5.550s 53.164us 20 20 100.00
intr_test 50 50 100.00
alert_handler_intr_test 2.480s 15.952us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
alert_handler_tl_errors 32.700s 1315.341us 20 20 100.00
tl_d_illegal_access 20 20 100.00
alert_handler_tl_errors 32.700s 1315.341us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
alert_handler_csr_hw_reset 12.910s 118.287us 5 5 100.00
alert_handler_csr_rw 13.270s 579.567us 20 20 100.00
alert_handler_csr_aliasing 338.950s 30270.710us 5 5 100.00
alert_handler_same_csr_outstanding 59.160s 2994.181us 20 20 100.00
tl_d_partial_access 50 50 100.00
alert_handler_csr_hw_reset 12.910s 118.287us 5 5 100.00
alert_handler_csr_rw 13.270s 579.567us 20 20 100.00
alert_handler_csr_aliasing 338.950s 30270.710us 5 5 100.00
alert_handler_same_csr_outstanding 59.160s 2994.181us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
alert_handler_shadow_reg_errors 326.740s 23172.209us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
alert_handler_shadow_reg_errors 326.740s 23172.209us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
alert_handler_shadow_reg_errors 326.740s 23172.209us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
alert_handler_shadow_reg_errors 326.740s 23172.209us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
alert_handler_shadow_reg_errors_with_csr_rw 1246.020s 71876.027us 20 20 100.00
tl_intg_err 25 25 100.00
alert_handler_sec_cm 43.250s 1261.096us 5 5 100.00
alert_handler_tl_intg_err 101.090s 7699.418us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
alert_handler_tl_intg_err 101.090s 7699.418us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
alert_handler_shadow_reg_errors 326.740s 23172.209us 20 20 100.00
sec_cm_ping_timer_config_regwen 50 50 100.00
alert_handler_smoke 63.030s 3292.496us 50 50 100.00
sec_cm_alert_config_regwen 50 50 100.00
alert_handler_smoke 63.030s 3292.496us 50 50 100.00
sec_cm_alert_loc_config_regwen 50 50 100.00
alert_handler_smoke 63.030s 3292.496us 50 50 100.00
sec_cm_class_config_regwen 50 50 100.00
alert_handler_smoke 63.030s 3292.496us 50 50 100.00
sec_cm_alert_intersig_diff 50 50 100.00
alert_handler_sig_int_fail 67.340s 1907.445us 50 50 100.00
sec_cm_lpg_intersig_mubi 48 50 96.00
alert_handler_lpg 3505.230s 259416.692us 48 50 96.00
sec_cm_esc_intersig_diff 50 50 100.00
alert_handler_sig_int_fail 67.340s 1907.445us 50 50 100.00
sec_cm_alert_rx_intersig_bkgn_chk 49 50 98.00
alert_handler_entropy 3269.280s 59129.444us 49 50 98.00
sec_cm_esc_tx_intersig_bkgn_chk 49 50 98.00
alert_handler_entropy 3269.280s 59129.444us 49 50 98.00
sec_cm_esc_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 43.250s 1261.096us 5 5 100.00
sec_cm_ping_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 43.250s 1261.096us 5 5 100.00
sec_cm_esc_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 43.250s 1261.096us 5 5 100.00
sec_cm_ping_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 43.250s 1261.096us 5 5 100.00
sec_cm_esc_timer_fsm_global_esc 5 5 100.00
alert_handler_sec_cm 43.250s 1261.096us 5 5 100.00
sec_cm_accu_ctr_redun 5 5 100.00
alert_handler_sec_cm 43.250s 1261.096us 5 5 100.00
sec_cm_esc_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 43.250s 1261.096us 5 5 100.00
sec_cm_ping_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 43.250s 1261.096us 5 5 100.00
sec_cm_ping_timer_lfsr_redun 5 5 100.00
alert_handler_sec_cm 43.250s 1261.096us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 50 52.00
alert_handler_stress_all_with_rand_reset 614.740s 10428.687us 26 50 52.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 66275175223572598873390088621206284570873106724858053050451329517148146590714 84
UVM_ERROR @ 134489391 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 134489391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 103833274917497106756240662261314360128548093673581625362793193332107837733115 368
UVM_ERROR @ 90407921300 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 90407921300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 65597904417738324545444099819774902695185497298844775899057573814402434896818 122
UVM_ERROR @ 2295061741 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2295061741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 113478931084941321996351771796235759340190133251823687569292074380198284535513 219
UVM_ERROR @ 7298260057 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7298260057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 41536585530798295989280207825983059873876640453352158749576555307713335301744 164
UVM_ERROR @ 2860146331 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2860146331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 4109130482330134072511818126062280494016744101145556897413804040091580772460 160
UVM_ERROR @ 2477761149 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2477761149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 72028826638383378886854892047124044605855948906052437991027281417797353931512 212
UVM_ERROR @ 9310686129 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9310686129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 12078965599243004496818600195254492959834702269070223620430072119492336260810 123
UVM_ERROR @ 9819394350 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9819394350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 107569895783847817512723315630941594026544034746511724233381264305671382886249 150
UVM_ERROR @ 49380518972 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 49380518972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 31483479706723376065309443427561947928660930119389985373457759478621519310538 101
UVM_ERROR @ 1783194768 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1783194768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 85509728842237850919264199212637375639837703821349671713112200944879520773130 148
UVM_ERROR @ 8670105908 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8670105908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 106104415591032025287829564957497893773352345015130521538428773381674940230357 83
UVM_ERROR @ 127968559 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 127968559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 87028754111388550772114819272385618904070955031929507822856203771073239517801 121
UVM_ERROR @ 898114026 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 898114026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 27231507973280097776745005380541613441365186098290898248658485267510593770052 94
UVM_ERROR @ 364893011 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 364893011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 70770237134466704470471115588382335669128165474502024928972116666353205099487 85
UVM_ERROR @ 110384513 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 110384513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 87347993709076110906966735264650643939622721856623191713960499996753394321002 91
UVM_ERROR @ 933066107 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 933066107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 81603479509195919275435668685661776839301907342674334093935670152405785929627 88
UVM_ERROR @ 355835879 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 355835879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 98695475045541306776068508131633306646434437586448261842062103906409365667412 111
UVM_ERROR @ 4619611089 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4619611089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 23449679932848286862044004954991989293218085750372565129692021826164822650033 125
UVM_ERROR @ 1784304743 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1784304743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 22437197880321121811471536194441062847033817042002376287550315558159272940931 162
UVM_ERROR @ 6097151832 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6097151832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 80192057006643466301773114744522027863513045387501674463856984539457722985254 138
UVM_ERROR @ 3328518546 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3328518546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 55146730647651511605189196829182477795736513043220712339660170170246524041672 96
UVM_ERROR @ 683469114 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 683469114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 35063510995774931588314371133535551964938287787214048311865281779285117104904 90
UVM_ERROR @ 503590098 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 503590098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_lpg 22093192815164153172514903242537194373020127465775937362682575621943545681450 85
UVM_ERROR @ 218836062048 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 218836062048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 99531836100246981154044105992401197391498879207005494532578815772240664486931 87
UVM_ERROR @ 1297421971 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 1297421971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 4569381032672788644251069736444349236733969419363663877008927407205480141723 108
UVM_ERROR @ 13023098646 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 13023098646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 83298972824006101469817973147506674747979771460699412362680399309073045045943 105
UVM_ERROR @ 14224328755 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 14224328755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 57830426782373846362629432912426319698041228516552180637999743065189690316361 96
UVM_ERROR @ 25000486365 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 25000486365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 86211191010267476335710225884604789960400480196853717549580483400276335118645 86
UVM_ERROR @ 4116219028 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 4116219028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all 39748110553407402411096613280776470815107554583066601215476732202892347112353 236
UVM_ERROR @ 26139334802 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (11 [0xb] vs 15 [0xf]) reg name: intr_state
UVM_INFO @ 26139334802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 10141857483219051352149943920936486371750924055093816848810279294495069341983 97
UVM_ERROR @ 4517913424 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 4517913424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 111484484517067997829636231775477626709594847454632093356492751793678949746832 90
UVM_ERROR @ 2444055766 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 2444055766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 13476410911706502445944013606633803325804035109558375699476086251542053117287 102
UVM_ERROR @ 4445533611 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 4445533611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 14101156437080460248532943042278840880608108247903915591503127235011968288257 117
UVM_ERROR @ 7897716974 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 7897716974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 44603757608785503539166434008484060065375504276006032178232839773914667519178 114
UVM_ERROR @ 6138413963 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 6138413963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 60895334141036173446809306288357143880054982204283781400337411498115362922763 102
UVM_ERROR @ 28896662241 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 28896662241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 14034870002765885831031648548884920754795179444375841300299556696000118538839 108
UVM_ERROR @ 12390344448 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 12390344448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 109472494950493572710891483417702043854140960095116235751659514525561815817681 142
UVM_ERROR @ 26731722837 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 26731722837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 108561859602886811597608371692828105133871761742663004801638261079276193405132 87
UVM_ERROR @ 1535801335 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 1535801335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 34673664313663773540891015086566051391487410433207051357674668915149406730411 93
UVM_ERROR @ 2556718506 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 2556718506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 112071961322579205862000803804827918457875554339578586878876780946281287657805 96
UVM_ERROR @ 10354176599 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 10354176599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 111230952280509919381311700450099924824669387790424416088029309050323477697069 123
UVM_ERROR @ 10841423938 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 10841423938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 39102815066309634475615632579465209104334656412509906752851342926690107833146 129
UVM_ERROR @ 28502800515 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 28502800515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 70352516888334317399945151968468355514585916957567534784163557861851079255607 126
UVM_ERROR @ 16046224979 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 16046224979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 39981655956799400670074654323577772299936265705180080836508277884355442107717 90
UVM_ERROR @ 34650567464 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 34650567464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 66655952860104522736657192393053076343389744891862717081666904825480297111699 102
UVM_ERROR @ 4809884675 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 4809884675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 64902738464227667584700777559042145246667177399131744434383240894758394143329 153
UVM_ERROR @ 18359613372 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 18359613372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 23402390597622841513392137845388499544175054786578295996368597927106876707759 84
UVM_ERROR @ 3809712381 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 3809712381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 111736919009627965210761913248411018988639968275768948782831429188931557585330 133
UVM_ERROR @ 27147293786 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 27147293786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 59797186443009201805426979157801352386963424047887212478502509808931312154205 90
UVM_ERROR @ 2384179794 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 2384179794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 92173339733687700937360894214870076814068589371148304264287525763950230030161 128
UVM_ERROR @ 38814152958 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 38814152958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 44468097562657360047683764307597794141313018266248589495172611603623409926567 93
UVM_ERROR @ 2025604354 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
UVM_INFO @ 2025604354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
alert_handler_entropy 29254795067844622692569139589973291933008457416231908589805213248242092015133 80
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model.
alert_handler_ping_timeout 69379071772056236672991683656486913412483535155993188394852283579322860949356 80
UVM_ERROR @ 1123146960 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 1123146960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 76864862320403143283259494785952249674287745453785079316485567835675025697748 80
UVM_ERROR @ 200659127 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 200659127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 4080999532444827256929357888529783167117495546422778574628353585533410059270 80
UVM_ERROR @ 331858486 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 331858486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 114023534694623158284855795342816598014370781695936430874917892479389753046553 80
UVM_ERROR @ 1008813676 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 1008813676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_lpg 96339575957222342002073152111940396785615640477510144287183842425161264395313 80
UVM_ERROR @ 5146332101 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.
UVM_INFO @ 5146332101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state
alert_handler_stress_all_with_rand_reset 81211654662443751055559325678042532773108284548519962745592078180392705922401 111
UVM_ERROR @ 5104085051 ps: (alert_handler_scoreboard.sv:490) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 3 [0x3]) reg name: alert_handler_reg_block.classb_state
UVM_INFO @ 5104085051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---