Simulation Results: edn/edn0

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.40 %
  • code
  • 95.74 %
  • assert
  • 97.61 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.20 %
  • toggle
  • 97.12 %
  • FSM
  • 91.94 %
Validation stages
V1
100.00%
V2
98.97%
V2S
100.00%
V3
82.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.260s 38.929us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.820s 16.956us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.930s 95.743us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.360s 1524.331us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.300s 188.837us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.350s 62.615us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.930s 95.743us 20 20 100.00
edn_csr_aliasing 1.300s 188.837us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 6.850s 1253.332us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 6.850s 1253.332us 300 300 100.00
genbits 300 300 100.00
edn_genbits 6.850s 1253.332us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.490s 22.272us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.630s 40.800us 200 200 100.00
errs 100 100 100.00
edn_err 1.560s 95.462us 100 100 100.00
disable 90 100 90.00
edn_disable 1.270s 13.791us 50 50 100.00
edn_disable_auto_req_mode 14.310s 500.000us 40 50 80.00
stress_all 50 50 100.00
edn_stress_all 4.830s 319.656us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.920s 19.315us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.370s 82.603us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.930s 446.406us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.930s 446.406us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.820s 16.956us 5 5 100.00
edn_csr_rw 0.930s 95.743us 20 20 100.00
edn_csr_aliasing 1.300s 188.837us 5 5 100.00
edn_same_csr_outstanding 1.240s 55.989us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.820s 16.956us 5 5 100.00
edn_csr_rw 0.930s 95.743us 20 20 100.00
edn_csr_aliasing 1.300s 188.837us 5 5 100.00
edn_same_csr_outstanding 1.240s 55.989us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 2.330s 133.591us 20 20 100.00
edn_sec_cm 6.500s 717.682us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.920s 23.623us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.630s 40.800us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.500s 717.682us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.500s 717.682us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 6.500s 717.682us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 6.500s 717.682us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.630s 40.800us 200 200 100.00
edn_sec_cm 6.500s 717.682us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.630s 40.800us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.330s 133.591us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 41 50 82.00
edn_stress_all_with_rand_reset 93.020s 33440.288us 41 50 82.00

Error Messages

   Test seed line log context
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 98848775749551585176762466090514057839784613268982746315588240828444003425811 88
UVM_FATAL @ 9387096 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x0061b6c2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 9387096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 43172677117462556636216798484481673376448971371497751896593387023531108559186 88
UVM_FATAL @ 14636885 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00c0a9c2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 14636885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 100322590801784414717064250678594470025434099049117180837689372015446306145356 88
UVM_FATAL @ 33515735 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000962 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 33515735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 112920729232551749793025208835458886746478391289123986009775343336230077746495 88
UVM_FATAL @ 38027208 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000692 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 38027208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 111123971336079037181501036470498779866015814606492517933894775042589510826803 88
UVM_FATAL @ 72790449 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00001963 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 72790449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 98748122525597803801398656770347613685387410647838577194102675798912298699724 88
UVM_FATAL @ 18575316 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 18575316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 3364515163882807616665641019078905058099217072321937426291039043523833904249 88
UVM_FATAL @ 12680093 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000692 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 12680093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 55337725200735336751314556023681187014498184464355992202134663999621761168024 205
UVM_ERROR @ 1447050598 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1447050598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 47496554136672705020025640065846606501994645160562130107883034197413314007001 208
UVM_ERROR @ 944186048 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 944186048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 100032855687998632575048830065486515812761822640180632143896994862537183936537 241
UVM_ERROR @ 2662134331 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2662134331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 15049149310810108548024888767147056466114759604607517600891167098486996792134 138
UVM_ERROR @ 1059632346 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1059632346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 19074043668821816925466490225012863798674289469933550951939079788061463784509 319
UVM_ERROR @ 2480080479 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2480080479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 93689424347836655488713412719592943325009148868908727112545892312926520512203 180
UVM_ERROR @ 922610374 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 922610374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 113648226209984067876481324707308480837552369753443497365356016684265859306531 316
UVM_ERROR @ 3159663225 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3159663225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 110254483262120206703243684684555249911403978177794958851718980488879173561139 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 98098615845979297703453853348689567269539621834064318377545954332180248848731 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 95644532467541802781223734724916206825893174238580130767258928565720556673847 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit
edn_stress_all_with_rand_reset 102134377802090444045881252842396711845832251105351741456592096112870556602404 218
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 666247198 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup
edn_stress_all_with_rand_reset 2304634620701560541397839537617925881421134655645839743231399391885904594204 199
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1888546007 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup