Simulation Results: edn/edn1

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.18 %
  • code
  • 95.95 %
  • assert
  • 97.14 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.08 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
99.38%
V2S
99.57%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.400s 19.162us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.800s 45.546us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.880s 46.605us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.130s 360.117us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.200s 41.075us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.240s 135.207us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.880s 46.605us 20 20 100.00
edn_csr_aliasing 1.200s 41.075us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 92.280s 9464.116us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 92.280s 9464.116us 300 300 100.00
genbits 300 300 100.00
edn_genbits 92.280s 9464.116us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.350s 23.685us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.450s 54.543us 200 200 100.00
errs 100 100 100.00
edn_err 1.370s 58.040us 100 100 100.00
disable 94 100 94.00
edn_disable 1.190s 17.048us 50 50 100.00
edn_disable_auto_req_mode 5.050s 500.000us 44 50 88.00
stress_all 50 50 100.00
edn_stress_all 4.650s 261.228us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.840s 21.181us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.300s 28.817us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.530s 128.037us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.530s 128.037us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.800s 45.546us 5 5 100.00
edn_csr_rw 0.880s 46.605us 20 20 100.00
edn_csr_aliasing 1.200s 41.075us 5 5 100.00
edn_same_csr_outstanding 1.150s 143.450us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.800s 45.546us 5 5 100.00
edn_csr_rw 0.880s 46.605us 20 20 100.00
edn_csr_aliasing 1.200s 41.075us 5 5 100.00
edn_same_csr_outstanding 1.150s 143.450us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 24 25 96.00
edn_sec_cm 4.400s 788.134us 4 5 80.00
edn_tl_intg_err 2.980s 349.291us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.260s 30.899us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.450s 54.543us 200 200 100.00
sec_cm_main_sm_fsm_sparse 4 5 80.00
edn_sec_cm 4.400s 788.134us 4 5 80.00
sec_cm_ack_sm_fsm_sparse 4 5 80.00
edn_sec_cm 4.400s 788.134us 4 5 80.00
sec_cm_fifo_ctr_redun 4 5 80.00
edn_sec_cm 4.400s 788.134us 4 5 80.00
sec_cm_ctr_redun 4 5 80.00
edn_sec_cm 4.400s 788.134us 4 5 80.00
sec_cm_main_sm_ctr_local_esc 204 205 99.51
edn_alert 1.450s 54.543us 200 200 100.00
edn_sec_cm 4.400s 788.134us 4 5 80.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.450s 54.543us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.980s 349.291us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 40 50 80.00
edn_stress_all_with_rand_reset 73.320s 5222.489us 40 50 80.00

Error Messages

   Test seed line log context
UVM_FATAL (alert_receiver_driver.sv:218) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
edn_sec_cm 90573821111302610882729799104431486558172072278857761948655430655729417071449 148
UVM_FATAL @ 157541924 ps: (alert_receiver_driver.sv:218) [uvm_test_top.env.m_alert_agent_fatal_alert.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 157541924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 36183786134101146659656183607753791605719689515648578448450398821585309270563 277
UVM_ERROR @ 2861291644 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2861291644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 72916407167004319018728464415005520086578904708368415371606882020761918310318 384
UVM_ERROR @ 3173472512 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3173472512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 57799051937809739759893156830323194330668317454567704980230455025403372859732 218
UVM_ERROR @ 2144426449 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2144426449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 37121197035999234391505553233354746254399989453433230701391982181941687881200 163
UVM_ERROR @ 854773047 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 854773047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 11699637567408907202030665840132689871845211019259493955642291485371987232312 263
UVM_ERROR @ 2614412011 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2614412011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 29062661778325089189860742664734514327174741538384651668948078864272563079241 144
UVM_ERROR @ 1002300445 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1002300445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 13763739971355489388294279139293011773573080902794392666669768265483934188639 176
UVM_ERROR @ 1969676014 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1969676014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 67821576860753565001940745839791875245545451997658768949143900943912902374955 260
UVM_ERROR @ 1274636635 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1274636635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 95168471135778578712140828641401759980704514286015900179920905603584749340789 135
UVM_ERROR @ 853846941 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 853846941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 16988366739083844348972619229961253949283753626168880715864969159526826579029 125
UVM_ERROR @ 120704699 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 120704699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 35688271653054274413149436471875756665693630489775217922734664457090768544816 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 21890725877121739016494187884427310898197158932511927713627888883166183136279 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 39904331141108953439644367869619202141249596365529488757683807380442877136256 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 50101949403181661599277758286782447244829593087472394844317874651251304843967 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 4489816096583661683805110734439843353880811961655874043905734009961728988857 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 95862643798784687732447287138829514827334990538869938375858577338926948513429 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---