Simulation Results: kmac/unmasked

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.40 %
  • code
  • 92.05 %
  • assert
  • 97.90 %
  • func
  • 96.25 %
  • line
  • 97.65 %
  • branch
  • 95.93 %
  • cond
  • 94.75 %
  • toggle
  • 100.00 %
  • FSM
  • 71.90 %
Validation stages
V1
100.00%
V2
98.31%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 76.420s 47655.359us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.370s 62.017us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.530s 27.660us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 16.530s 11952.317us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 5.540s 798.853us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.920s 84.619us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.530s 27.660us 20 20 100.00
kmac_csr_aliasing 5.540s 798.853us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.090s 121.084us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 2.020s 230.562us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 2912.170s 494332.565us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1002.380s 158132.133us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1917.970s 180070.127us 5 5 100.00
kmac_test_vectors_sha3_256 1851.260s 85742.318us 5 5 100.00
kmac_test_vectors_sha3_384 1344.970s 188407.241us 5 5 100.00
kmac_test_vectors_sha3_512 603.010s 16331.116us 5 5 100.00
kmac_test_vectors_shake_128 2261.020s 471005.139us 5 5 100.00
kmac_test_vectors_shake_256 1893.690s 89057.129us 5 5 100.00
kmac_test_vectors_kmac 2.960s 159.530us 5 5 100.00
kmac_test_vectors_kmac_xof 2.780s 74.015us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 344.450s 15932.005us 50 50 100.00
app 50 50 100.00
kmac_app 370.580s 69009.556us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 312.490s 126445.829us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 341.930s 19281.819us 50 50 100.00
error 49 50 98.00
kmac_error 385.650s 91383.790us 49 50 98.00
key_error 49 50 98.00
kmac_key_error 12.270s 3594.979us 49 50 98.00
sideload_invalid 39 50 78.00
kmac_sideload_invalid 151.430s 10111.765us 39 50 78.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 39.310s 5699.205us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 34.090s 1578.234us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 75.110s 30293.913us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 31.410s 2367.861us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2055.320s 305910.547us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.180s 45.433us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.320s 183.490us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.440s 204.742us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.440s 204.742us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.370s 62.017us 5 5 100.00
kmac_csr_rw 1.530s 27.660us 20 20 100.00
kmac_csr_aliasing 5.540s 798.853us 5 5 100.00
kmac_same_csr_outstanding 2.890s 403.520us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.370s 62.017us 5 5 100.00
kmac_csr_rw 1.530s 27.660us 20 20 100.00
kmac_csr_aliasing 5.540s 798.853us 5 5 100.00
kmac_same_csr_outstanding 2.890s 403.520us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.840s 933.470us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.840s 933.470us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.840s 933.470us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.840s 933.470us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 5.450s 481.859us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 75.080s 22407.166us 5 5 100.00
kmac_tl_intg_err 5.460s 379.083us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.460s 379.083us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 31.410s 2367.861us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 76.420s 47655.359us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 344.450s 15932.005us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.840s 933.470us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 75.080s 22407.166us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 75.080s 22407.166us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 75.080s 22407.166us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 76.420s 47655.359us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 31.410s 2367.861us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 75.080s 22407.166us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 271.770s 47864.034us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 76.420s 47655.359us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
kmac_stress_all_with_rand_reset 123.990s 4242.439us 6 10 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 61822577127825068012727869792949183078922287563627698032223090176246784367153 198
UVM_ERROR @ 4488327088 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 4488327088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 44849213166391249112972278730476404805014228472618839212933856122322901948835 100
UVM_ERROR @ 16500215056 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16500215056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 104294585367575391199796994791315861679030526163392964268514077850696066076095 197
UVM_ERROR @ 4242439319 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4242439319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 3765980148714054800024653132755907796869209197153509544089822663894815369756 94
UVM_ERROR @ 7740362703 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7740362703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 49674057750532735793839315920519544732206397448523508127297621557581077505657 79
UVM_FATAL @ 10048324290 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x20b29000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10048324290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
kmac_sideload_invalid 84177189581476511508538799886593124985578690075778104641962482290099024646245 84
UVM_FATAL @ 10073824499 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbe5fc000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10073824499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)
kmac_sideload_invalid 50114692303500338712619489733991427593188036169665634969991367362328324567612 89
UVM_FATAL @ 10254644518 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8269d000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10254644518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set!
kmac_key_error 108907143361653287309453516023263271955793176543315404092740207840635232356934 105
UVM_ERROR @ 2166617877 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
UVM_INFO @ 2166617877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)
kmac_sideload_invalid 82989946020330507410594685260987952558352061277282183763115401087966579541828 88
UVM_FATAL @ 10179161031 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4a095000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10179161031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24)
kmac_sideload_invalid 15860710150310899593090915369622770753570304330771746440036426401835200674461 104
UVM_FATAL @ 10111765047 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x81805000, Comparison=CompareOpEq, exp_data=0x1, call_count=24)
UVM_INFO @ 10111765047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13)
kmac_sideload_invalid 27511913133218930497479311258639774869371539245976794155084335900480348222954 90
UVM_FATAL @ 10089241405 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3f9ce000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10089241405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22)
kmac_sideload_invalid 96359324503308291526935464946026506779798463193574388846609734409716553512747 100
UVM_FATAL @ 10333829250 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x34cc7000, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 10333829250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)
kmac_sideload_invalid 39750676183025334545401236748405432793740880797516426375241245575909022200966 86
UVM_FATAL @ 10224250466 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x85571000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10224250466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16)
kmac_sideload_invalid 83653237182679295098131555777074527988394586983749250568994212178493506604432 94
UVM_FATAL @ 10324726540 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9d94000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10324726540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)
kmac_sideload_invalid 4135294361445058669044943940309134904554098529142399816413171247181282661966 84
UVM_FATAL @ 10079179562 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd8db9000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10079179562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 81899698386110102188084731679365738789987851481741295733507556617623134047863 78
UVM_FATAL @ 10016276532 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe0c00000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10016276532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_error 73439255360494632971131516043778085890473419844553516285206350605694305633332 182
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---