Simulation Results: lc_ctrl/volatile_unlock_disabled

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.73 %
  • code
  • 88.65 %
  • assert
  • 96.13 %
  • func
  • 96.40 %
  • line
  • 97.90 %
  • branch
  • 96.99 %
  • cond
  • 82.46 %
  • toggle
  • 91.35 %
  • FSM
  • 74.55 %
Validation stages
V1
100.00%
V2
99.86%
V2S
99.72%
V3
46.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 11.900s 760.701us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.180s 17.573us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.260s 19.459us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.000s 44.155us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.550s 466.066us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.670s 27.823us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.260s 19.459us 20 20 100.00
lc_ctrl_csr_aliasing 1.550s 466.066us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 8.980s 122.436us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 16.530s 349.589us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.390s 13.311us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 5.370s 487.914us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 14.420s 795.794us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 15.760s 561.968us 50 50 100.00
security_escalation 260 260 100.00
lc_ctrl_state_failure 14.420s 795.794us 50 50 100.00
lc_ctrl_prog_failure 5.370s 487.914us 50 50 100.00
lc_ctrl_errors 15.760s 561.968us 50 50 100.00
lc_ctrl_security_escalation 13.440s 1167.524us 50 50 100.00
lc_ctrl_jtag_state_failure 70.490s 3267.881us 20 20 100.00
lc_ctrl_jtag_prog_failure 21.820s 6808.806us 20 20 100.00
lc_ctrl_jtag_errors 64.430s 15574.094us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_csr_hw_reset 3.960s 1720.504us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.200s 341.601us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 38.450s 9568.957us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 20.360s 1021.392us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.490s 221.246us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 6.120s 335.147us 10 10 100.00
lc_ctrl_jtag_alert_test 2.860s 134.704us 10 10 100.00
lc_ctrl_jtag_smoke 15.400s 4380.818us 20 20 100.00
lc_ctrl_jtag_state_post_trans 20.530s 2093.396us 20 20 100.00
lc_ctrl_jtag_prog_failure 21.820s 6808.806us 20 20 100.00
lc_ctrl_jtag_errors 64.430s 15574.094us 20 20 100.00
lc_ctrl_jtag_access 14.000s 740.746us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 21.600s 3941.633us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 18.320s 741.492us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.490s 56.512us 50 50 100.00
stress_all 49 50 98.00
lc_ctrl_stress_all 371.900s 31863.204us 49 50 98.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.760s 34.963us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 3.950s 127.019us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 3.950s 127.019us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.180s 17.573us 5 5 100.00
lc_ctrl_csr_rw 1.260s 19.459us 20 20 100.00
lc_ctrl_csr_aliasing 1.550s 466.066us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.110s 155.414us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.180s 17.573us 5 5 100.00
lc_ctrl_csr_rw 1.260s 19.459us 20 20 100.00
lc_ctrl_csr_aliasing 1.550s 466.066us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.110s 155.414us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 5.740s 314.844us 20 20 100.00
lc_ctrl_sec_cm 9.220s 2277.112us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 5.740s 314.844us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 16.530s 349.589us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 14.420s 795.794us 50 50 100.00
lc_ctrl_sec_cm 9.220s 2277.112us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 14.420s 795.794us 50 50 100.00
lc_ctrl_sec_cm 9.220s 2277.112us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.420s 795.794us 50 50 100.00
lc_ctrl_sec_cm 9.220s 2277.112us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 14.420s 795.794us 50 50 100.00
lc_ctrl_sec_cm 9.220s 2277.112us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 14.420s 795.794us 50 50 100.00
lc_ctrl_sec_cm 9.220s 2277.112us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.420s 795.794us 50 50 100.00
lc_ctrl_sec_cm 9.220s 2277.112us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 14.420s 795.794us 50 50 100.00
lc_ctrl_sec_cm 9.220s 2277.112us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 14.420s 795.794us 50 50 100.00
lc_ctrl_sec_cm 9.220s 2277.112us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 13.440s 1167.524us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 8.980s 122.436us 50 50 100.00
lc_ctrl_jtag_state_post_trans 20.530s 2093.396us 20 20 100.00
sec_cm_intersig_mubi 49 50 98.00
lc_ctrl_sec_mubi 16.450s 724.686us 49 50 98.00
sec_cm_token_valid_ctrl_mubi 49 50 98.00
lc_ctrl_sec_mubi 16.450s 724.686us 49 50 98.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 21.900s 2601.745us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 16.080s 2361.455us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 16.080s 2361.455us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 23 50 46.00
lc_ctrl_stress_all_with_rand_reset 131.320s 22961.905us 23 50 46.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all 52719668945344277094795869544476341885542176707250809466980490226895652567192 1946
UVM_ERROR @ 1206598640 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1206598640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 77367599506287260169273161197322142665116253541842114029525412449432142450875 5988
UVM_ERROR @ 14355770558 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 14355770558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 33209137433487167451979934685781245401518250678599656361975369207788054009193 11345
UVM_ERROR @ 11335678628 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 11335678628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 100159750068403543826498055056501210869797220103123092146972030447715214459115 604
UVM_ERROR @ 1638152898 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1638152898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 21735879262887029889595763042206298913330283505990880156469660344758036364300 7256
UVM_ERROR @ 3979971548 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3979971548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 26772431878694428661067424342558207517173328297762296350832164518851737039424 1337
UVM_ERROR @ 1126747737 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1126747737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 10512030743194756928198056692082108972440984881537321248810757997162901302721 151
UVM_ERROR @ 599909988 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 599909988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 44598918315409122309972939730612149386388473291397982028038540061151443885864 7830
UVM_ERROR @ 2376382625 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2376382625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 21903988631341162822107122941116167869522426803862228569540298470847027134163 3116
UVM_ERROR @ 1209834900 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1209834900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 5110024548402257850962615966451557958477021276657409158497946575020147842829 194
UVM_ERROR @ 409721510 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 409721510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 104772383765342466991148137088156172925840518175216179158785767643274065084537 2214
UVM_ERROR @ 1157045114 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1157045114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 89486236519623193826546140888331958401102525055316864780050083593611291869046 1966
UVM_ERROR @ 14576608885 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14576608885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 71162183151891094081744792581008207760437755742675360212124437030704359241398 7287
UVM_ERROR @ 31076473755 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 31076473755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 49798741034149837484289479763568340332675046017266345274994106696262831082656 8175
UVM_ERROR @ 9186153705 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9186153705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 109238880867822618699604673003666171163382449836385549207374122720001240172964 5799
UVM_ERROR @ 2091852165 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2091852165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 29895537918667203856593769915929891259765133431133080574997163780566488338154 7470
UVM_ERROR @ 13720320035 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 13720320035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 27461433591428628984320982187069836800409192548127831126690206300306364455565 471
UVM_ERROR @ 1300767152 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1300767152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 55133573585701447825162419028504640622118401682676215070341948843140053674467 2172
UVM_ERROR @ 12080195047 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12080195047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 30112212069472689299093751467859112154522922224882501255423761439884818796108 1958
UVM_ERROR @ 6594283187 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6594283187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 59471362826611651212130779246351429491835611426761329133255527258091727975133 2411
UVM_ERROR @ 1311276988 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1311276988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 2965626255916482018222518177129025288623844443896522680370803844417259295731 7876
UVM_ERROR @ 3018516752 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3018516752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 24663934150047920503105794130109869905423989135242291642645216118248830670663 2260
UVM_ERROR @ 1350293692 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1350293692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 104529532382796789655376169903852353707953891454823317014667397899064740200231 2260
UVM_ERROR @ 8105395490 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8105395490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91592995376521030106717508204550984116743343510920799404260314339982368010008 325
UVM_ERROR @ 11911464856 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11911464856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 105941188780055376148903035382149512285170903229722597931724598108364897846411 247
UVM_ERROR @ 1218506227 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1218506227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 30455201461206024051159354991420976799264955063987900508970305453643785036034 1365
UVM_ERROR @ 759552362 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 759552362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked*
lc_ctrl_stress_all_with_rand_reset 63625542352376425029472606238484265029351618166279866840650229189342889448296 13472
UVM_ERROR @ 3062439144 ps: (lc_ctrl_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 105, LC_St DecLcStTestUnlocked4
UVM_INFO @ 3062439144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (alert_receiver_driver.sv:218) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
lc_ctrl_stress_all_with_rand_reset 10703034140874941644166617993830775572502789998713459449373282267421520395506 2157
UVM_FATAL @ 839197518 ps: (alert_receiver_driver.sv:218) [uvm_test_top.env.m_alert_agent_fatal_state_error.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 839197518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_sec_mubi 65413497707726033146717810219065640839466818478392704059804929355615837150350 1634
UVM_ERROR @ 133985827 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_sec_mubi_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 133985827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---