Simulation Results: otbn

 
01/05/2026 16:00:28 DVSim: v1.17.3 sha: 1521b5f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.95 %
  • code
  • 96.70 %
  • assert
  • 97.15 %
  • func
  • 100.00 %
  • block
  • 99.51 %
  • line
  • 99.66 %
  • branch
  • 93.75 %
  • toggle
  • 93.39 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
96.74%
V2S
94.40%
V3
30.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 15.000s 133.311us 1 1 100.00
single_binary 100 100 100.00
otbn_single 92.000s 339.497us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 6.000s 24.935us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 5.000s 19.688us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 7.000s 454.932us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 5.000s 22.929us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 15.000s 82.482us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 5.000s 19.688us 20 20 100.00
otbn_csr_aliasing 5.000s 22.929us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 89.000s 5218.761us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 45.000s 1372.395us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 56.000s 144.489us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 61.000s 531.861us 1 1 100.00
back_to_back 9 10 90.00
otbn_multi 186.000s 1996.648us 9 10 90.00
stress_all 10 10 100.00
otbn_stress_all 95.000s 608.143us 10 10 100.00
lc_escalation 57 60 95.00
otbn_escalate 25.000s 173.778us 57 60 95.00
zero_state_err_urnd 0 5 0.00
otbn_zero_state_err_urnd 11.000s 10.690us 0 5 0.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 24.000s 72.549us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 6.000s 18.013us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 5.000s 18.796us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 8.000s 48.545us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 8.000s 48.545us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 6.000s 24.935us 5 5 100.00
otbn_csr_rw 5.000s 19.688us 20 20 100.00
otbn_csr_aliasing 5.000s 22.929us 5 5 100.00
otbn_same_csr_outstanding 7.000s 27.838us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 6.000s 24.935us 5 5 100.00
otbn_csr_rw 5.000s 19.688us 20 20 100.00
otbn_csr_aliasing 5.000s 22.929us 5 5 100.00
otbn_same_csr_outstanding 7.000s 27.838us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 12.000s 22.820us 10 10 100.00
otbn_dmem_err 13.000s 20.188us 15 15 100.00
internal_integrity 15 17 88.24
otbn_alu_bignum_mod_err 21.000s 44.022us 5 5 100.00
otbn_controller_ispr_rdata_err 14.000s 334.489us 5 5 100.00
otbn_mac_bignum_acc_err 20.000s 45.183us 5 5 100.00
otbn_urnd_err 12.000s 14.143us 0 2 0.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 9.000s 13.134us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 11.000s 27.881us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 11.000s 47.168us 9 10 90.00
tl_intg_err 25 25 100.00
otbn_sec_cm 364.000s 2108.344us 5 5 100.00
otbn_tl_intg_err 32.000s 216.469us 20 20 100.00
passthru_mem_tl_intg_err 15 20 75.00
otbn_passthru_mem_tl_intg_err 69.000s 379.123us 15 20 75.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 364.000s 2108.344us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 364.000s 2108.344us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 15.000s 133.311us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 13.000s 20.188us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 12.000s 22.820us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 32.000s 216.469us 20 20 100.00
sec_cm_controller_fsm_global_esc 57 60 95.00
otbn_escalate 25.000s 173.778us 57 60 95.00
sec_cm_controller_fsm_local_esc 35 40 87.50
otbn_imem_err 12.000s 22.820us 10 10 100.00
otbn_dmem_err 13.000s 20.188us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 10.690us 0 5 0.00
otbn_illegal_mem_acc 9.000s 13.134us 5 5 100.00
otbn_sec_cm 364.000s 2108.344us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 364.000s 2108.344us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 92.000s 339.497us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 35 40 87.50
otbn_imem_err 12.000s 22.820us 10 10 100.00
otbn_dmem_err 13.000s 20.188us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 10.690us 0 5 0.00
otbn_illegal_mem_acc 9.000s 13.134us 5 5 100.00
otbn_sec_cm 364.000s 2108.344us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 364.000s 2108.344us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 57 60 95.00
otbn_escalate 25.000s 173.778us 57 60 95.00
sec_cm_start_stop_ctrl_fsm_local_esc 35 40 87.50
otbn_imem_err 12.000s 22.820us 10 10 100.00
otbn_dmem_err 13.000s 20.188us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 10.690us 0 5 0.00
otbn_illegal_mem_acc 9.000s 13.134us 5 5 100.00
otbn_sec_cm 364.000s 2108.344us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 364.000s 2108.344us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 92.000s 339.497us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 11.000s 77.990us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 11.000s 13.894us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 115.000s 962.261us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 115.000s 962.261us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 9 10 90.00
otbn_rf_base_intg_err 13.000s 2075.966us 9 10 90.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 364.000s 2108.344us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 364.000s 2108.344us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 16.000s 381.049us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 364.000s 2108.344us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 364.000s 2108.344us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 73.000s 225.254us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 73.000s 225.254us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 12.000s 67.435us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 92.000s 339.497us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 92.000s 339.497us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 92.000s 339.497us 100 100 100.00
sec_cm_write_mem_integrity 9 10 90.00
otbn_multi 186.000s 1996.648us 9 10 90.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 92.000s 339.497us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 92.000s 339.497us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 20.000s 953.965us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 92.000s 339.497us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 364.000s 2108.344us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
otbn_stress_all_with_rand_reset 357.000s 9358.718us 3 10 30.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 14.000s 64.006us 1 1 100.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
otbn_escalate 102486127226722622286714928767988538267194243047157354855799424138997125844576 None
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 102486127226722622286714928767988538267194243047157354855799424138997125844576 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_escalate/latest
2026/05/02 02:33:25 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
otbn_multi 114701083290215852194411861239395163988104920342154538038527697341367283622524 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 74425092228622574325158428202858966135204545840333834339029184305910934808678 287
UVM_ERROR @ 2577921812 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2577921812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 45358572230598630610559701261964075492118146936463638332872590648966332913618 161
UVM_ERROR @ 968548397 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 968548397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 93169792076551757976340776974239157021551703581558032674339934366129451675670 408
UVM_ERROR @ 9358717650 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9358717650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 114593497296301778837739352538941658188027953553242593291740773603948382806549 163
UVM_ERROR @ 1675696918 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1675696918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_zero_state_err_urnd 55333878815272905735682409833217760843007785788341330649302280336832244443813 108
UVM_ERROR @ 10690212 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 10690212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 101415037748237759871133778224338917889096065041958218718194539219448698939611 112
UVM_ERROR @ 7113886 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 7113886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 34298484399827917710882614081708780136975927456406374374388468882506407741759 109
UVM_ERROR @ 32553860 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 32553860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 34458219052700628585432002327909260731118325723790793926510609770741230062960 105
UVM_ERROR @ 5923880 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 5923880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 23830368921447951292071140562402586190303321331075297037162791497517328564353 107
UVM_ERROR @ 7137430 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 7137430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_urnd_err 1271177275045188440743901089985033096405820419503177354142649402142278574977 109
UVM_ERROR @ 14142843 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 14142843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_urnd_err 47024627815696528895726617599938393480729433300570351599755298582697659601211 112
UVM_ERROR @ 28468668 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_INFO @ 28468668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:372) [csr_utils_pkg::csr_rd_sub.isolation_fork] Timeout waiting to csr_rd otbn_reg_block.status (addr=*)
otbn_rf_base_intg_err 104792939087815556958018878298287283032136678616705503809959214049826549040382 122
UVM_FATAL @ 2075965838 ps: (csr_utils_pkg.sv:372) [csr_utils_pkg::csr_rd_sub.isolation_fork] Timeout waiting to csr_rd otbn_reg_block.status (addr=0x517a0018)
UVM_INFO @ 2075965838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed
otbn_partial_wipe 77469351619863666852442548602680594280525722564193976611164135747554848124297 108
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 3034220 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 3034220 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 3034220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [otbn_imem_err_vseq] expect alert:fatal to fire
otbn_stress_all_with_rand_reset 12660180982847253239628376313567746462418386899143132892852009233496663662365 529
UVM_ERROR @ 938902825 ps: (cip_base_vseq.sv:1028) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] expect alert:fatal to fire
UVM_INFO @ 938902825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 71227008658571369027936342422501329946563419097877961299007390583154027702557 172
UVM_FATAL @ 325346891 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 325346891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_stack_addr_integ_chk 26241192361735293809264889801632289935113740678469687207021552596049839648401 114
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 56612416 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 56612416 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 56612416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 15862187551361107532870821090001892077569960030131551500622281988504380395084 113
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 8685462 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 8685462 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 8685462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 115220428941147664472073161880191578805696807177917442746769639661466958049749 313
UVM_FATAL @ 626608935 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 626608935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_escalate 40773184693177910977201007587834713824308578954188714412607499056171397371147 105
UVM_ERROR @ 1511982 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 1511982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 75804707291288440467943245274437990630619969989957156344015987119126079198375 91
UVM_FATAL @ 8921930 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 8921930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 34010579615615529008200448666074018380377344876132745306512124914923913371663 91
UVM_FATAL @ 10442003 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 10442003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn_rnd.sv,233): Assertion UrndNoReseedOnReset_A has failed
otbn_passthru_mem_tl_intg_err 71262631388239929684025145569801287352373599270241777257022510166636477792371 128
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_rnd.sv,233): (time 80358183 PS) Assertion tb.dut.u_otbn_core.u_otbn_rnd.UrndNoReseedOnReset_A has failed
UVM_ERROR @ 80358183 ps: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 80358183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 59250262263141629941818277455550538843789407720435734094474505712068583260293 91
UVM_FATAL @ 40091860 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 40091860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 46225226945419153584137703721324896591346831007165064725142872657909625782007 91
UVM_FATAL @ 44122902 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 44122902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---