Simulation Results: lc_ctrl/volatile_unlock_disabled

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.06 %
  • code
  • 93.58 %
  • assert
  • 96.11 %
  • func
  • 89.49 %
  • block
  • 96.75 %
  • line
  • 97.38 %
  • branch
  • 91.72 %
  • toggle
  • 89.97 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.45%
V2S
100.00%
V3
48.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 5.000s 255.458us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 20.000s 77.375us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 16.000s 25.460us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 21.000s 397.137us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 21.000s 42.512us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 17.000s 118.839us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 16.000s 25.460us 20 20 100.00
lc_ctrl_csr_aliasing 21.000s 42.512us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 5.000s 207.498us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 8.000s 340.362us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 20.000s 32.577us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 6.000s 676.375us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 9.000s 647.040us 50 50 100.00
lc_errors 49 50 98.00
lc_ctrl_errors 20.000s 760.529us 49 50 98.00
security_escalation 257 260 98.85
lc_ctrl_state_failure 9.000s 647.040us 50 50 100.00
lc_ctrl_prog_failure 6.000s 676.375us 50 50 100.00
lc_ctrl_errors 20.000s 760.529us 49 50 98.00
lc_ctrl_security_escalation 10.000s 683.054us 50 50 100.00
lc_ctrl_jtag_state_failure 61.000s 3502.781us 19 20 95.00
lc_ctrl_jtag_prog_failure 8.000s 687.146us 20 20 100.00
lc_ctrl_jtag_errors 43.000s 10942.827us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 12.000s 3885.909us 20 20 100.00
lc_ctrl_jtag_state_post_trans 18.000s 5390.759us 20 20 100.00
lc_ctrl_jtag_prog_failure 8.000s 687.146us 20 20 100.00
lc_ctrl_jtag_errors 43.000s 10942.827us 19 20 95.00
lc_ctrl_jtag_access 20.000s 1438.999us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 27.000s 1550.768us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 8.000s 489.673us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 308.852us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 27.000s 2531.290us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 17.000s 1173.421us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 73.117us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.000s 575.989us 10 10 100.00
lc_ctrl_jtag_alert_test 11.000s 217.023us 10 10 100.00
jtag_priority 9 10 90.00
lc_ctrl_jtag_priority 24.000s 1674.799us 9 10 90.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 12.746us 50 50 100.00
stress_all 50 50 100.00
lc_ctrl_stress_all 257.000s 202886.692us 50 50 100.00
alert_test 50 50 100.00
lc_ctrl_alert_test 20.000s 36.776us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 5.000s 176.127us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 5.000s 176.127us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 20.000s 77.375us 5 5 100.00
lc_ctrl_csr_rw 16.000s 25.460us 20 20 100.00
lc_ctrl_csr_aliasing 21.000s 42.512us 5 5 100.00
lc_ctrl_same_csr_outstanding 3.000s 170.964us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 20.000s 77.375us 5 5 100.00
lc_ctrl_csr_rw 16.000s 25.460us 20 20 100.00
lc_ctrl_csr_aliasing 21.000s 42.512us 5 5 100.00
lc_ctrl_same_csr_outstanding 3.000s 170.964us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 5.000s 249.200us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 278.837us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 4.000s 278.837us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 8.000s 340.362us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 9.000s 647.040us 50 50 100.00
lc_ctrl_sec_cm 5.000s 249.200us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 9.000s 647.040us 50 50 100.00
lc_ctrl_sec_cm 5.000s 249.200us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 9.000s 647.040us 50 50 100.00
lc_ctrl_sec_cm 5.000s 249.200us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 9.000s 647.040us 50 50 100.00
lc_ctrl_sec_cm 5.000s 249.200us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 9.000s 647.040us 50 50 100.00
lc_ctrl_sec_cm 5.000s 249.200us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 9.000s 647.040us 50 50 100.00
lc_ctrl_sec_cm 5.000s 249.200us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 9.000s 647.040us 50 50 100.00
lc_ctrl_sec_cm 5.000s 249.200us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 9.000s 647.040us 50 50 100.00
lc_ctrl_sec_cm 5.000s 249.200us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 10.000s 683.054us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 5.000s 207.498us 50 50 100.00
lc_ctrl_jtag_state_post_trans 18.000s 5390.759us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 11.000s 354.489us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 11.000s 354.489us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 13.000s 669.723us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 18.000s 767.619us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 18.000s 767.619us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 24 50 48.00
lc_ctrl_stress_all_with_rand_reset 101.000s 11391.926us 24 50 48.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 24 test runs
lc_ctrl_stress_all_with_rand_reset 26732614257257766660025694791969671171831199043278666344753432204742624703555 485
UVM_INFO @ 1418890602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 55813090223667145350086186478215964486970994352887441388495623599377553965443 579
UVM_INFO @ 318652506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 103126113007949594096129021502189805377607766939845551167052755414175992666034 215
UVM_INFO @ 681486140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96413449291113979404651199970705811613266190547460934879026077053108780879613 560
UVM_INFO @ 1114739929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 35016262953284911478490070639245653316261285680713931571041761327011712054398 3981
UVM_INFO @ 3139146332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 2752220261807451813614141258452760823175486431365584793604889580798476547789 174
UVM_INFO @ 1574450833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 26753937049917658030535451727905243834013688832054901400925327839622660451161 169
UVM_INFO @ 468332497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 19369541286561138734406884346903501840137628971622050012955533754005881172771 309
UVM_INFO @ 2494764725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91119663403267085470039368085292800022196875513128554894049561286006046066067 311
UVM_INFO @ 5264036805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 112477254780881937713236750105329303527793097612232122305180832839619433580789 347
UVM_INFO @ 8830132337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96765364554413326564838454585748521488832185579992803580208147700918220473051 1130
UVM_INFO @ 6637403081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 35139246564347833402405463680707723572680143809163126343956035520417333803526 2557
UVM_INFO @ 31253101803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75548368130249480057296765135788438517368829733698021258150748145608903515418 356
UVM_INFO @ 498781270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 50625786001723696052845667573537266004998489753442248274385680633809428597943 1432
UVM_INFO @ 2609149753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 113770466353466687399803893441731192557232953060320890888795183794086540487365 2468
UVM_INFO @ 3927339443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 45308670357981753752512646493053955872008421677089808494302522764156147258379 971
UVM_INFO @ 19304431343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 115730992273918919596118803767440568529791041846966697394374732254955197657791 3364
UVM_INFO @ 2501565788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 49429056533664608573624933993664444163482469289123930923390334354933439404307 511
UVM_INFO @ 8004458141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 78038550991006522303755913762171124979747909145840044421516829655416976180241 399
UVM_INFO @ 2565115074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 41117289998214245495839574499203111534257378115946196124566585208483408163552 650
UVM_INFO @ 2444502631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 46925602088598322728001307433917230883827245374215658644448833361918638709371 371
UVM_INFO @ 3643421064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 76139931144101424215765421472820391437027796461954458629357648396795217613330 173
UVM_INFO @ 881261113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 71733311789461621785408377967021296082088129042224392773972147109682431220294 2498
UVM_INFO @ 1311186004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 83923466292552206264236806002116982174510972722164782756338129150830076844160 1180
UVM_INFO @ 4961613232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_errors 47028028855242600915254012262054671050361433523168733279669979608526954609022 833
UVM_INFO @ 108633911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 69719259009144880341535623880221782587328545735255211663167830715711769860347 1222
UVM_INFO @ 8786032514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! 1 test run
lc_ctrl_jtag_priority 55773600115086480107686379950278977778894433238091464670962524217796611785527 157
UVM_INFO @ 10006871848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_failure 81451679134380367868581351260482931404244682912648148432988596026298090081697 177
UVM_INFO @ 1186581726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [lc_ctrl_common_vseq] wait timeout occurred! 1 test run
lc_ctrl_stress_all_with_rand_reset 110143040610169609093456681566065719354833101940262651587334721012965204838100 1907
UVM_INFO @ 11046494857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:246) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_cpu_en_o == exp_o.lc_cpu_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStProd 1 test run
lc_ctrl_stress_all_with_rand_reset 55907583687603344171993303060679071092812443179084999001491611056686781020968 3167
UVM_INFO @ 2039058061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---