Simulation Results: rom_ctrl/32kb

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.19 %
  • code
  • 94.61 %
  • assert
  • 97.67 %
  • func
  • 99.29 %
  • block
  • 96.73 %
  • line
  • 97.22 %
  • branch
  • 94.09 %
  • toggle
  • 87.12 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 4.000s 138.524us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 7.000s 552.118us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 5.000s 3832.323us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 6.000s 165.135us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 6.000s 292.260us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.000s 194.234us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 5.000s 3832.323us 20 20 100.00
rom_ctrl_csr_aliasing 6.000s 292.260us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 4.000s 175.722us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 4.000s 129.948us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 4.000s 139.066us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 17.000s 1130.230us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 8.000s 4126.672us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 8.000s 177.272us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 7.000s 2790.225us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 7.000s 2790.225us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.000s 552.118us 5 5 100.00
rom_ctrl_csr_rw 5.000s 3832.323us 20 20 100.00
rom_ctrl_csr_aliasing 6.000s 292.260us 5 5 100.00
rom_ctrl_same_csr_outstanding 5.000s 175.409us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.000s 552.118us 5 5 100.00
rom_ctrl_csr_rw 5.000s 3832.323us 20 20 100.00
rom_ctrl_csr_aliasing 6.000s 292.260us 5 5 100.00
rom_ctrl_same_csr_outstanding 5.000s 175.409us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.000s 15376.921us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.000s 840.919us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 141.000s 2854.997us 5 5 100.00
rom_ctrl_tl_intg_err 31.000s 343.714us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 141.000s 2854.997us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 141.000s 2854.997us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.000s 15376.921us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.000s 15376.921us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.000s 15376.921us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.000s 15376.921us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.000s 15376.921us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 141.000s 2854.997us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 141.000s 2854.997us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 4.000s 138.524us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 4.000s 138.524us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 4.000s 138.524us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 31.000s 343.714us 20 20 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.000s 15376.921us 20 20 100.00
rom_ctrl_kmac_err_chk 8.000s 4126.672us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.000s 15376.921us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.000s 15376.921us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.000s 15376.921us 20 20 100.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.000s 840.919us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 141.000s 2854.997us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 12 20 60.00
rom_ctrl_stress_all_with_rand_reset 123.000s 9086.566us 12 20 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 6 test runs
rom_ctrl_stress_all_with_rand_reset 111203868883607881215086577234754889974779276776478170538957522568683236496712 96
UVM_INFO @ 3000637748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 101819013456248238163882052737253949650938218682832446997963553360757570439367 93
UVM_INFO @ 11470238612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 73587622137293360162364012281004284488752064328063573018322922637364519159098 92
UVM_INFO @ 340252436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 90443080855559093008977338033627138566757398581875923975475545771573609854162 92
UVM_INFO @ 556817741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 4289306459303900174603268951492298965376816568785731378324369937637352292696 89
UVM_INFO @ 134063406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 55429010066084829229269266413763446348273523196055114608975449056934182733600 89
UVM_INFO @ 120887651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [rom_ctrl_common_vseq] wait timeout occurred! 1 test run
rom_ctrl_stress_all_with_rand_reset 47365245250335587449417489792339522316177511220197011938141665058978439368822 112
UVM_INFO @ 11268583405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:235) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 1 test run
rom_ctrl_stress_all_with_rand_reset 73164270735213793623429878273066303725565030852181161919326148464938784949372 129
UVM_INFO @ 9063614060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---