| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| unmapped |
|
96.77% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_memory_smoke | 25 | 25 | 100.00 | |||
| dma_memory_smoke | 8.000s | 1566.962us | 25 | 25 | 100.00 | |
| dma_handshake_smoke | 25 | 25 | 100.00 | |||
| dma_handshake_smoke | 8.000s | 1572.067us | 25 | 25 | 100.00 | |
| dma_generic_smoke | 50 | 50 | 100.00 | |||
| dma_generic_smoke | 9.000s | 862.958us | 50 | 50 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 28.902us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| dma_csr_rw | 2.000s | 19.842us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| dma_csr_bit_bash | 11.000s | 607.463us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| dma_csr_aliasing | 8.000s | 2015.252us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| dma_csr_mem_rw_with_rand_reset | 2.000s | 102.355us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| dma_csr_rw | 2.000s | 19.842us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 8.000s | 2015.252us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_memory_region_lock | 5 | 5 | 100.00 | |||
| dma_memory_region_lock | 99.000s | 26583.393us | 5 | 5 | 100.00 | |
| dma_memory_tl_error | 3 | 3 | 100.00 | |||
| dma_memory_stress | 685.000s | 55623.369us | 3 | 3 | 100.00 | |
| dma_handshake_tl_error | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 1673.000s | 144550.264us | 3 | 3 | 100.00 | |
| dma_handshake_stress | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 1673.000s | 144550.264us | 3 | 3 | 100.00 | |
| dma_memory_stress | 3 | 3 | 100.00 | |||
| dma_memory_stress | 685.000s | 55623.369us | 3 | 3 | 100.00 | |
| dma_generic_stress | 5 | 5 | 100.00 | |||
| dma_generic_stress | 1423.000s | 95007.829us | 5 | 5 | 100.00 | |
| dma_handshake_mem_buffer_overflow | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 1673.000s | 144550.264us | 3 | 3 | 100.00 | |
| dma_abort | 5 | 5 | 100.00 | |||
| dma_abort | 16.000s | 1731.882us | 5 | 5 | 100.00 | |
| dma_stress_all | 3 | 3 | 100.00 | |||
| dma_stress_all | 189.000s | 22113.417us | 3 | 3 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| dma_alert_test | 2.000s | 27.436us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| dma_intr_test | 2.000s | 17.106us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| dma_tl_errors | 5.000s | 441.402us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| dma_tl_errors | 5.000s | 441.402us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 28.902us | 1 | 1 | 100.00 | |
| dma_csr_rw | 2.000s | 19.842us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 8.000s | 2015.252us | 1 | 1 | 100.00 | |
| dma_same_csr_outstanding | 3.000s | 760.807us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 28.902us | 1 | 1 | 100.00 | |
| dma_csr_rw | 2.000s | 19.842us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 8.000s | 2015.252us | 1 | 1 | 100.00 | |
| dma_same_csr_outstanding | 3.000s | 760.807us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_illegal_addr_range | 13 | 13 | 100.00 | |||
| dma_mem_enabled | 28.000s | 702.959us | 5 | 5 | 100.00 | |
| dma_generic_stress | 1423.000s | 95007.829us | 5 | 5 | 100.00 | |
| dma_handshake_stress | 1673.000s | 144550.264us | 3 | 3 | 100.00 | |
| dma_config_lock | 15 | 15 | 100.00 | |||
| dma_config_lock | 12.000s | 1277.868us | 15 | 15 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| dma_tl_intg_err | 5.000s | 191.571us | 25 | 25 | 100.00 | |
| dma_sec_cm | 2.000s | 33.221us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 30 | 31 | 96.77 | |||
| dma_short_transfer | 227.000s | 21752.804us | 25 | 25 | 100.00 | |
| dma_longer_transfer | 138.000s | 22982.551us | 5 | 5 | 100.00 | |
| dma_stress_all_with_rand_reset | 16.000s | 2088.762us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| dma_stress_all_with_rand_reset | 91882038732284347788154365629917685249933053689118480397758530833922819199167 | 122 |
UVM_INFO @ 2088761504ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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