Simulation Results

Simulation Results: uart

06/06/2026 03:31:11 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
95.30 %

code
96.65 %

assert
98.56 %

func
90.69 %

block
99.08 %

line
99.52 %

branch
98.34 %

toggle
88.74 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		95.97%
V2S		100.00%
V3		85.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	uart_smoke	23.000s	10546.287us	10	10	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	1.000s	16.630us	1	1	100.00
csr_rw				5	5	100.00
	uart_csr_rw	2.000s	13.017us	5	5	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	3.000s	526.573us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	2.000s	20.962us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	uart_csr_mem_rw_with_rand_reset	2.000s	56.559us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	uart_csr_rw	2.000s	13.017us	5	5	100.00
	uart_csr_aliasing	2.000s	20.962us	1	1	100.00

381/397 passed

95.97 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				10	10	100.00
	uart_tx_rx	87.000s	64504.285us	10	10	100.00
parity				20	20	100.00
	uart_smoke	23.000s	10546.287us	10	10	100.00
	uart_tx_rx	87.000s	64504.285us	10	10	100.00
parity_error				20	20	100.00
	uart_intr	364.000s	229431.536us	10	10	100.00
	uart_rx_parity_err	615.000s	176590.610us	10	10	100.00
watermark				20	20	100.00
	uart_tx_rx	87.000s	64504.285us	10	10	100.00
	uart_intr	364.000s	229431.536us	10	10	100.00
fifo_full				10	10	100.00
	uart_fifo_full	550.000s	285721.085us	10	10	100.00
fifo_overflow				10	10	100.00
	uart_fifo_overflow	199.000s	98726.429us	10	10	100.00
fifo_reset				199	200	99.50
	uart_fifo_reset	461.000s	311543.687us	199	200	99.50
rx_frame_err				10	10	100.00
	uart_intr	364.000s	229431.536us	10	10	100.00
rx_break_err				10	10	100.00
	uart_intr	364.000s	229431.536us	10	10	100.00
rx_timeout				10	10	100.00
	uart_intr	364.000s	229431.536us	10	10	100.00
perf				10	10	100.00
	uart_perf	572.000s	19505.803us	10	10	100.00
sys_loopback				10	10	100.00
	uart_loopback	17.000s	8344.967us	10	10	100.00
line_loopback				10	10	100.00
	uart_loopback	17.000s	8344.967us	10	10	100.00
rx_noise_filter				0	10	0.00
	uart_noise_filter	63.000s	201689.342us	0	10	0.00
rx_start_bit_filter				10	10	100.00
	uart_rx_start_bit_filter	81.000s	38241.652us	10	10	100.00
tx_overide				10	10	100.00
	uart_tx_ovrd	31.000s	7183.892us	10	10	100.00
rx_oversample				10	10	100.00
	uart_rx_oversample	66.000s	7039.520us	10	10	100.00
long_b2b_transfer				9	10	90.00
	uart_long_xfer_wo_dly	786.000s	130634.889us	9	10	90.00
stress_all				6	10	60.00
	uart_stress_all	875.000s	193540.714us	6	10	60.00
alert_test				10	10	100.00
	uart_alert_test	2.000s	82.412us	10	10	100.00
intr_test				10	10	100.00
	uart_intr_test	2.000s	17.083us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	uart_tl_errors	3.000s	79.564us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	uart_tl_errors	3.000s	79.564us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	uart_csr_hw_reset	1.000s	16.630us	1	1	100.00
	uart_csr_rw	2.000s	13.017us	5	5	100.00
	uart_csr_aliasing	2.000s	20.962us	1	1	100.00
	uart_same_csr_outstanding	2.000s	23.076us	5	5	100.00
tl_d_partial_access				12	12	100.00
	uart_csr_hw_reset	1.000s	16.630us	1	1	100.00
	uart_csr_rw	2.000s	13.017us	5	5	100.00
	uart_csr_aliasing	2.000s	20.962us	1	1	100.00
	uart_same_csr_outstanding	2.000s	23.076us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	uart_sec_cm	2.000s	100.258us	5	5	100.00
	uart_tl_intg_err	2.000s	87.108us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	uart_tl_intg_err	2.000s	87.108us	25	25	100.00

17/20 passed

85.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				17	20	85.00
	uart_stress_all_with_rand_reset	64.000s	15378.791us	17	20	85.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:				7 test runs
	uart_noise_filter	41455805927872009305540748692334831287945652366513203410347325793318932445849	95	UVM_ERROR @ 94338632343 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 94338672343 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (48 [0x30] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 94421112343 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark UVM_ERROR @ 94421112343 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
	uart_stress_all	65578194576164948188752666675670530779271836718914919700398829584130274910611	98	UVM_ERROR @ 137274273671 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 137274690341 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (57 [0x39] vs 127 [0x7f]) reg name: uart_reg_block.rdata UVM_ERROR @ 137274732008 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 137275023677 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (57 [0x39] vs 110 [0x6e]) reg name: uart_reg_block.rdata
	uart_stress_all	109393588735859303632172601534668008704335303689075735052281820046671594816931	191	UVM_ERROR @ 165586953181 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 165587116445 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (62 [0x3e] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 165816808485 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 165816828893 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_noise_filter	47056442642867173701333014887646879192145347133813752729983929762860845142103	83	UVM_ERROR @ 72275104 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 72566773 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 317735401 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr UVM_ERROR @ 317735401 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
	uart_noise_filter	8376184445090144990515896949438262172890101697489311616943480485992465424170	88	UVM_ERROR @ 74026577874 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 74027012654 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (152 [0x98] vs 251 [0xfb]) reg name: uart_reg_block.rdata UVM_ERROR @ 74027056132 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 74027230044 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (152 [0x98] vs 251 [0xfb]) reg name: uart_reg_block.rdata
	uart_stress_all	15642928255577695594603302532090147886463882562178703513246796235537187717926	98	UVM_ERROR @ 136434741839 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 136434923659 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (245 [0xf5] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 136493060604 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 136493106059 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_noise_filter	947990402943413966602148897655592981949746484749307851941075453008708646607	85	UVM_ERROR @ 32488476369 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 32488518036 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata UVM_ERROR @ 33282857724 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 33282899391 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				5 test runs
	uart_noise_filter	52077194587008364910052856703460330677122352358272080043987729929545965428344	83	UVM_ERROR @ 18334342 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 21542701 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 33459463 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 35167810 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
	uart_noise_filter	76941928695305181591578315907784840737491761778552102820584405308443359222902	83	UVM_ERROR @ 326583740 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 326583740 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 1393596167 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (205 [0xcd] vs 154 [0x9a]) reg name: uart_reg_block.rdata UVM_ERROR @ 1651661364 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_stress_all	110962117660465355806597656799056709241600170109414238695349511111553874401508	92	UVM_ERROR @ 57427720245 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 59392220245 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 10, clk_pulses: 0 UVM_ERROR @ 59393345245 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (75 [0x4b] vs 175 [0xaf]) reg name: uart_reg_block.rdata UVM_ERROR @ 59614720245 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
	uart_noise_filter	11891627156224708952035353387364100553054239426690166318395800641376594209569	92	UVM_ERROR @ 201652925004 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 201652925004 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 201659008313 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 201659008313 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_stress_all_with_rand_reset	37845678792525162268505307988920376253001032218279740167917634882878777725694	179	UVM_INFO @ 11087301047 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Issuing reset for run 7/10 UVM_INFO @ 11087461047 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Stress w/ reset is done for run 7/10
UVM_ERROR (uart_scoreboard.sv:379) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [] vs []) check rx_empty fail: uart_rx_clk_pulses = , rx_q.size = *				4 test runs
	uart_long_xfer_wo_dly	33009892968333046839370793693815408239623487196503623734210963199017301155707	86	UVM_ERROR @ 21385735191 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1 UVM_ERROR @ 21631678335 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1 UVM_ERROR @ 21928504239 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1 UVM_ERROR @ 22061564127 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
	uart_noise_filter	91779891658897827845912130451735415047216215381561209091838432579972926554382	83	UVM_ERROR @ 371747167 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 379907167 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 379907167 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 388687167 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
	uart_noise_filter	61342772717451005690758341540669418463104615727364404028605870693848957515712	86	UVM_ERROR @ 2241822624 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 2246873124 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 2246873124 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 2248277163 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
	uart_noise_filter	76998019807632118560471745004566630206716350167402820678100037842538693763739	83	UVM_ERROR @ 84684054 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 84684054 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 151775026 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 5, clk_pulses: 0 UVM_ERROR @ 151795644 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (40 [0x28] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:448) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [] vs [*]) Interrupt_pin: TxWatermark				1 test run
	uart_stress_all_with_rand_reset	68345306057830169379073364670348619184386161469150947355989760085688160578110	212	UVM_INFO @ 42834471671 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/892 UVM_INFO @ 44248871671 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/892 UVM_INFO @ 44956071671 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/892 UVM_INFO @ 45894471671 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/892
UVM_ERROR (uart_scoreboard.sv:446) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [] vs [*]) Interrupt: RxParityErr				1 test run
	uart_stress_all_with_rand_reset	5055699372868331556482620974197353552343408250529934903517884467054713157426	179	UVM_ERROR @ 8755725075 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark UVM_ERROR @ 8755725075 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark UVM_INFO @ 8993725075 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/138 UVM_ERROR @ 9008485075 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR (uart_scoreboard.sv:446) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [] vs [*]) Interrupt: RxWatermark				1 test run
	uart_fifo_reset	39780197042556922056169612172874054586172287570485069046670301070308125719534	83	UVM_INFO @ 926524959 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/7 UVM_INFO @ 1723192055 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/7 UVM_INFO @ 8443791351 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/7 UVM_INFO @ 37937106423 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/7