| V1 |
|
100.00% |
| V2 |
|
92.99% |
| V2S |
|
90.00% |
| V3 |
|
35.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 40 | 40 | 100.00 | |||
| gpio_smoke | 2.100s | 110.016us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 2.010s | 290.147us | 10 | 10 | 100.00 | |
| gpio_smoke_en_cdc_prim | 2.170s | 77.028us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 2.600s | 117.278us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.980s | 34.538us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| gpio_csr_rw | 1.110s | 101.748us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 6.660s | 805.274us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 1.650s | 132.420us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.310s | 184.315us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| gpio_csr_rw | 1.110s | 101.748us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 1.650s | 132.420us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 20 | 20 | 100.00 | |||
| gpio_random_dout_din | 2.030s | 370.947us | 10 | 10 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.820s | 80.530us | 10 | 10 | 100.00 | |
| out_in_regs_read_write | 10 | 10 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 1.450s | 52.465us | 10 | 10 | 100.00 | |
| gpio_interrupt_programming | 10 | 10 | 100.00 | |||
| gpio_intr_rand_pgm | 1.910s | 417.929us | 10 | 10 | 100.00 | |
| random_interrupt_trigger | 10 | 10 | 100.00 | |||
| gpio_rand_intr_trigger | 3.160s | 464.782us | 10 | 10 | 100.00 | |
| interrupt_and_noise_filter | 10 | 10 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 4.430s | 1792.409us | 10 | 10 | 100.00 | |
| noise_filter_stress | 10 | 10 | 100.00 | |||
| gpio_filter_stress | 23.290s | 591.636us | 10 | 10 | 100.00 | |
| regs_long_reads_and_writes | 10 | 10 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 8.150s | 1057.263us | 10 | 10 | 100.00 | |
| full_random | 10 | 10 | 100.00 | |||
| gpio_full_random | 1.640s | 446.307us | 10 | 10 | 100.00 | |
| stress_all | 0 | 10 | 0.00 | |||
| gpio_stress_all | 62.560s | 16618.491us | 0 | 10 | 0.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| gpio_alert_test | 0.920s | 17.995us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| gpio_intr_test | 0.950s | 70.080us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 4.550s | 200.092us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 4.550s | 200.092us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 11 | 12 | 91.67 | |||
| gpio_csr_rw | 1.110s | 101.748us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.730s | 31.132us | 4 | 5 | 80.00 | |
| gpio_csr_aliasing | 1.650s | 132.420us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.980s | 34.538us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 11 | 12 | 91.67 | |||
| gpio_csr_rw | 1.110s | 101.748us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.730s | 31.132us | 4 | 5 | 80.00 | |
| gpio_csr_aliasing | 1.650s | 132.420us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.980s | 34.538us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 27 | 30 | 90.00 | |||
| gpio_tl_intg_err | 3.150s | 162.518us | 22 | 25 | 88.00 | |
| gpio_sec_cm | 1.360s | 161.616us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 22 | 25 | 88.00 | |||
| gpio_tl_intg_err | 3.150s | 162.518us | 22 | 25 | 88.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 7 | 10 | 70.00 | |||
| gpio_rand_straps | 0.890s | 23.822us | 7 | 10 | 70.00 | |
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 15.490s | 591.276us | 0 | 10 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 50 | 50 | 100.00 | |||
| gpio_inp_prd_cnt | 0.930s | 12.237us | 50 | 50 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 13 test runs | |||
| gpio_stress_all | 39968158602177965888291762664614210923840021902942980419957821341853508808792 | 76 |
UVM_INFO @ 160733504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 50428481660089211961047997796927148622290706692483820958590464775705763171348 | 821 |
UVM_INFO @ 16618490625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_rand_straps | 67846293206132122265343245088576806995154989134698100735901068908648924171471 | 75 |
UVM_INFO @ 1194950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 60775200111593131710609941331914257515095673149166114437974833748157974759123 | 1082 |
UVM_INFO @ 6334119601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 115194661527379175244482129202876800303468852144497488649055516238559235020580 | 77 |
UVM_INFO @ 268223037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 100974566788014444487259685579225437346340279972476175428848547953381684695216 | 738 |
UVM_INFO @ 5356398559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_rand_straps | 54909335232677965647356629529345516484711613788205429438794131006874191754964 | 75 |
UVM_INFO @ 2930784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 21392634741107285572012937556572179180884973129176111551729878810409405767635 | 376 |
UVM_INFO @ 2509289632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 37885201602371804739797304878855681815226031052549099069364460441545517157181 | 1474 |
UVM_INFO @ 77503782910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 16049721515579902833715287317087184321611414883400179009451215239652560435766 | 84 |
UVM_INFO @ 1354117500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 91480015255487580134860245328861271208901597714752771251824030529783537651753 | 1051 |
UVM_INFO @ 3034307586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 44833214852084008457169253201809560984663813737836836714840827273578969305446 | 599 |
UVM_INFO @ 2941604391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_rand_straps | 110082001695457840174535793980469174323665413337181227910869755886321700535639 | 75 |
UVM_INFO @ 4907697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 6 test runs | |||
| gpio_stress_all_with_rand_reset | 35617050436694396701751916270727243300879551740331835248833087008205468846351 | 349 |
UVM_INFO @ 591276166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 99459401251432312966943884600295272021480017749269657486704379530742408093445 | 290 |
UVM_INFO @ 666873603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 68303161596253241241023187557897585186026653839947587065901480295449940169633 | 78 |
UVM_INFO @ 2316407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 3347220555324764373308488388587846883363197950731022687477149388917298666719 | 168 |
UVM_INFO @ 149472573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 36850822096854708265097885932909503145022729247317518351759437843860744087122 | 124 |
UVM_INFO @ 628717075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 85094703347003002871883723969402214441973630982117173741354581757606639794937 | 79 |
UVM_INFO @ 266746527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done) | 4 test runs | |||
| gpio_stress_all_with_rand_reset | 20664152245421664603082982939134475284052539981553094352451191583601872829657 | 80 |
UVM_INFO @ 51600263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 42081277546680867457678735536111900216042103383833940776099876915103499437315 | 140 |
UVM_INFO @ 45130520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 3103076973667829827787075973504906621353012925795841121073441294226977939686 | 80 |
UVM_INFO @ 2275964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 37541435518990761592516509400930726541334432683019684686241887640342126760169 | 80 |
UVM_INFO @ 12021155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_* reset value: * | 2 test runs | |||
| gpio_tl_intg_err | 94936966811130426964529402816212581848073841828307933502378915257634182327935 | 135 |
UVM_INFO @ 44260395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_tl_intg_err | 13642083414765995670754515655655793302326555932585175721962051480842887356685 | 137 |
UVM_INFO @ 81652184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:660) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 1 test run | |||
| gpio_same_csr_outstanding | 9090862318342987495980741932984801502256794857407638099098871446097880910230 | 79 |
UVM_INFO @ 17084766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_*.enable reset value: * | 1 test run | |||
| gpio_tl_intg_err | 56916459273006521189565313808718828271077804712091560914786813697409075238410 | 212 |
UVM_INFO @ 207288135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|