Simulation Results: sram_ctrl/main

 
12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.27 %
  • code
  • 96.91 %
  • assert
  • 98.10 %
  • func
  • 96.80 %
  • block
  • 96.30 %
  • line
  • 97.05 %
  • branch
  • 94.50 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
94.59%
V2
84.91%
V2S
100.00%
V3
87.50%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 8.000s 2796.912us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 18.612us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 16.235us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 102.393us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.021us 1 1 100.00
csr_mem_rw_with_rand_reset 3 5 60.00
sram_ctrl_csr_mem_rw_with_rand_reset 11.000s 10004.702us 3 5 60.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 16.235us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 19.021us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 310.000s 53683.409us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 140.000s 33652.432us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 51.000s 11043.230us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 248.000s 19428.581us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 199.000s 17513.837us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 99.000s 66525.207us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 54.000s 13128.299us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 53.000s 23040.101us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 7.000s 1294.103us 8 8 100.00
sram_ctrl_partial_access_b2b 317.000s 58783.756us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 7.000s 2345.286us 0 8 0.00
sram_ctrl_throughput_w_partial_write 7.000s 1650.527us 0 8 0.00
sram_ctrl_throughput_w_readback 8.000s 4737.035us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 16.000s 4559.397us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 5.000s 1400.032us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 488.000s 34820.543us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 29.006us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 142.071us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 142.071us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 18.612us 1 1 100.00
sram_ctrl_csr_rw 2.000s 16.235us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 19.021us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 64.956us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 18.612us 1 1 100.00
sram_ctrl_csr_rw 2.000s 16.235us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 19.021us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 64.956us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 46.000s 30641.302us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 364.888us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 285.199us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 364.888us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 285.199us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 16.000s 4559.397us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 16.000s 4559.397us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 16.235us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 53.000s 23040.101us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 53.000s 23040.101us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 53.000s 23040.101us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 54.000s 13128.299us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 8.000s 2733.640us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 46.000s 30641.302us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 6.000s 2779.216us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 8.000s 2796.912us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 8.000s 2796.912us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 53.000s 23040.101us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 364.888us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 54.000s 13128.299us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 364.888us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 364.888us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 8.000s 2796.912us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 364.888us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 8 87.50
sram_ctrl_stress_all_with_rand_reset 35.000s 1735.074us 7 8 87.50

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 19426655871427028901120431133840930280690206643554805337659126903003748551651 86
UVM_INFO @ 672024014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 77780234098893029606557139328881718035444277992770467523816683483809931625299 86
UVM_INFO @ 1650527358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 1149257991450926868351481600348719947477841811507842062746711003464468582345 86
UVM_INFO @ 2345286165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 33122746089085818749623554782205137596963788235593574486206465269473632457047 86
UVM_INFO @ 2753136620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 98290296377228962268268353896125569283794552947597215829266575717289275610824 86
UVM_INFO @ 758039051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 14669202507011224077647472259189994870281859680043885608654341567000065008292 86
UVM_INFO @ 5487746442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 76806059261217083702134130962942400497700533817658088220535785472120541934264 86
UVM_INFO @ 1879023436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 41943128616201994253400972581946055894395751708126422085980216328428245810785 86
UVM_INFO @ 694871005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 1683416264168749052410831851854713811678048640000263836746172226006831154392 86
UVM_INFO @ 5497831719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 33634765389942680252739660550024614676057284682639711149982430019189462471150 86
UVM_INFO @ 4398070836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 19270694703933527658255482406110586248220709942347588555985646998380555022990 86
UVM_INFO @ 701789187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 107284842878012678726114673288746127035503390975733262563541050355770529551387 86
UVM_INFO @ 3001092477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 44752957606140373742227230142255846319524772293221589666915420070662697447085 86
UVM_INFO @ 710663922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 47506509220325941342552265676594883615944086100705336623633995045898782386467 86
UVM_INFO @ 693856449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 71488750503255704281754211159060935694742577834343790167051811895518377949431 86
UVM_INFO @ 1380935844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 80465037194640741260337897946578189333997786136766692288082714815575992715051 86
UVM_INFO @ 692568323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 53179159471257593218848131913133945789714138113176844130968426839207808898753 86
UVM_INFO @ 663796382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 56740192492935505914059146834210426318586760900212804220576371922132806410857 86
UVM_INFO @ 2767255417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 74825853577549173879376605299708483045205488158986104473860047655346400051412 86
UVM_INFO @ 2551480643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 27160017110680452277758200524657151858568938471020535829817875205819587565443 86
UVM_INFO @ 685419649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 87120563114958305743039366268167124291243276380337176942889123014786605170887 86
UVM_INFO @ 2856277571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 104101502972438766988166332088497354842904139577151474994086095161054731919817 86
UVM_INFO @ 4737035144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 97010238032728740384115751782688841565897820848966617450250534371375028338488 86
UVM_INFO @ 2464509979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 102999818377258018205638831102592813798425366464101442441723965323097948844358 86
UVM_INFO @ 691299720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done 2 test runs
sram_ctrl_csr_mem_rw_with_rand_reset 57986363031038458248158883567700131637399211929023318083722030002921743009165 85
UVM_INFO @ 10007560495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_csr_mem_rw_with_rand_reset 97365623817818130813515729898457448013781683170396256189077712501596498435965 85
UVM_INFO @ 10004701789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_stress_all_with_rand_reset 9005284109678347520253301822725945739283343588548346497335662060747771372515 98
UVM_INFO @ 108001903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---