Simulation Results: sram_ctrl/ret

 
12/06/2026 15:00:31 DVSim: v1.49.0 sha: e804155 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.79 %
  • code
  • 83.50 %
  • assert
  • 98.08 %
  • func
  • 96.80 %
  • block
  • 94.03 %
  • line
  • 95.21 %
  • branch
  • 89.83 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
94.59%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 3.000s 231.278us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 14.242us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 14.005us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 267.049us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 71.052us 1 1 100.00
csr_mem_rw_with_rand_reset 3 5 60.00
sram_ctrl_csr_mem_rw_with_rand_reset 20.000s 10002.160us 3 5 60.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 14.005us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 71.052us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 10.000s 1069.262us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 7.000s 508.596us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 16.000s 2105.835us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 216.000s 3686.146us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 9.000s 2257.136us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 25.000s 2911.509us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 9.000s 3142.614us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 17.000s 15332.332us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 3.000s 64.383us 8 8 100.00
sram_ctrl_partial_access_b2b 296.000s 81817.005us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 56.410us 0 8 0.00
sram_ctrl_throughput_w_partial_write 2.000s 424.096us 0 8 0.00
sram_ctrl_throughput_w_readback 2.000s 58.384us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 14.000s 964.053us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 3.000s 79.758us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 87.000s 5400.664us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 34.848us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 801.972us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 801.972us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 14.242us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.005us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 71.052us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 78.783us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 14.242us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.005us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 71.052us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 78.783us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 420.886us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 8.000s 207.404us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 1751.246us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 8.000s 207.404us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 1751.246us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 14.000s 964.053us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 14.000s 964.053us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 14.005us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 17.000s 15332.332us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 17.000s 15332.332us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 17.000s 15332.332us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 9.000s 3142.614us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 66.261us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 420.886us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 133.828us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 231.278us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 231.278us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 17.000s 15332.332us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 8.000s 207.404us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 9.000s 3142.614us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 8.000s 207.404us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 8.000s 207.404us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 3.000s 231.278us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 8.000s 207.404us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 88.000s 20887.417us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 101023067758614746865797841879428008476021605395610652116679720414716892381938 86
UVM_INFO @ 56410357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 80383754109710121286951134792688731475939371847547368684870184390490672681415 86
UVM_INFO @ 424095779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 75587888088930830932971875108538266272360384295248788569721618862516718233049 86
UVM_INFO @ 22560159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 8719040614216926377153418059082807044158803698841156140459521871550961885049 86
UVM_INFO @ 30590146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 100695690556854681779827982562081569449767591333129272614494041097144091144987 86
UVM_INFO @ 24772661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 28202485477495114757255969947246665138412732693984847063152348671449358138592 86
UVM_INFO @ 277783050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 33499165360284147852604654176687701838087919854774099057330534884504029975121 86
UVM_INFO @ 48523434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 40781672419818978121212618475377330575502654452381273581477009191812463051519 86
UVM_INFO @ 24948848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 47660427414263668973992414400927753813351237199292465608977242066579518290767 86
UVM_INFO @ 52787651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 43325033659722807503512297486394525164847530003293326098545019337450456373249 86
UVM_INFO @ 30935768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 64799272719978795195942267192755434477623453611245001508781402461272150714277 86
UVM_INFO @ 101844424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 100425767626517846231545135329329807692852408017359776042576928153152420058681 86
UVM_INFO @ 26513389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 51913291678636278245571532931455818981306002945425568998697658544977024297991 86
UVM_INFO @ 24162091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 22821228745912450482437234029063669482994756594931083509881981086738569151747 86
UVM_INFO @ 99965388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 35115372758616246995703864533605980300123904445985191225772499529506367780180 86
UVM_INFO @ 64383044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 101895041335902279880472162475981967451634277397111857738962568862345509172259 86
UVM_INFO @ 26289552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 83366239781541573009987945545819002827084845851092367837152595938460873535102 86
UVM_INFO @ 58384127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 66441479557677998284665077351196042200110974166206580654364577542315921177051 86
UVM_INFO @ 45085453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 71067916192089528511208541784508265259808024837725790720800728354172809309119 86
UVM_INFO @ 66013878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 91951826340080386204896729838347538703031513098579337288667088930886398594705 86
UVM_INFO @ 127930822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 108296422096070507723070778072513912547091495380576756194566192746206555378058 86
UVM_INFO @ 59574447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 107808435232736422083470493077195188448878949030034408371098141587682906434533 86
UVM_INFO @ 120393248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 73657947710252651088918609812633952188089828995948496122974334271130444442223 86
UVM_INFO @ 243161053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 61547620755423301885139884845173355670940983200444804006044095910806225757904 86
UVM_INFO @ 33649370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 20830943643961522088069791632118529928473185067460868937150043630435543504563 88
UVM_INFO @ 94277926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 46253001119660136132396130697833330665047289088176549764572686229011418374720 85
UVM_INFO @ 10002160492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---