Simulation Results: rom_ctrl/64kb

 
19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.91 %
  • code
  • 94.01 %
  • assert
  • 97.67 %
  • func
  • 99.06 %
  • block
  • 96.76 %
  • line
  • 97.24 %
  • branch
  • 94.09 %
  • toggle
  • 84.70 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 8.000s 2878.870us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.000s 290.046us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 9.000s 3993.292us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.000s 1031.245us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 8.000s 351.438us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.000s 2124.575us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 9.000s 3993.292us 5 5 100.00
rom_ctrl_csr_aliasing 8.000s 351.438us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.000s 1069.512us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.000s 1030.879us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 9.000s 989.575us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 35.000s 9700.286us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 12.000s 544.198us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 8.000s 2781.807us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 12.000s 509.695us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 12.000s 509.695us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 7.000s 290.046us 1 1 100.00
rom_ctrl_csr_rw 9.000s 3993.292us 5 5 100.00
rom_ctrl_csr_aliasing 8.000s 351.438us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.000s 362.783us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 7.000s 290.046us 1 1 100.00
rom_ctrl_csr_rw 9.000s 3993.292us 5 5 100.00
rom_ctrl_csr_aliasing 8.000s 351.438us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.000s 362.783us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 169.000s 42057.570us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 31.000s 6126.755us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 271.000s 1092.002us 5 5 100.00
rom_ctrl_tl_intg_err 82.000s 749.191us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 271.000s 1092.002us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 271.000s 1092.002us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 169.000s 42057.570us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 169.000s 42057.570us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 169.000s 42057.570us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 169.000s 42057.570us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 169.000s 42057.570us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 271.000s 1092.002us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 271.000s 1092.002us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 8.000s 2878.870us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 8.000s 2878.870us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 8.000s 2878.870us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 82.000s 749.191us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 169.000s 42057.570us 20 20 100.00
rom_ctrl_kmac_err_chk 12.000s 544.198us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 169.000s 42057.570us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 169.000s 42057.570us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 169.000s 42057.570us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 31.000s 6126.755us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 271.000s 1092.002us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 15 20 75.00
rom_ctrl_stress_all_with_rand_reset 132.000s 10645.905us 15 20 75.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 3 test runs
rom_ctrl_stress_all_with_rand_reset 97336288797412584761090513116563948889859901006308154915179761386221472910042 94
UVM_INFO @ 998672864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 63961026121714532119730164446927038986807983397578184246942219884888903524848 92
UVM_INFO @ 417077915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 85504676763024202556558084597344221094366627648479394623749238936166316796356 90
UVM_INFO @ 195686784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 70697747982699058818455556497131172881859050718476224525968926019810492153418 88
UVM_INFO @ 1654754250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 87351925061125991942273190497707699981414969427625293462321843904159328707449 88
UVM_INFO @ 989574967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
rom_ctrl_stress_all_with_rand_reset 16115805813569402625819033815380313626769924694094185182629573274367536345118 91
UVM_INFO @ 282582718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:235) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 1 test run
rom_ctrl_stress_all_with_rand_reset 95021320070674416843117371442758616150391619825120514193082970428335363364590 115
UVM_INFO @ 1929505881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---