Simulation Results: sram_ctrl/ret

 
19/06/2026 15:00:30 DVSim: v1.49.0 sha: c0022c1 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.46 %
  • code
  • 82.50 %
  • assert
  • 98.08 %
  • func
  • 96.80 %
  • block
  • 94.03 %
  • line
  • 95.21 %
  • branch
  • 89.83 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
97.30%
V2
84.91%
V2S
100.00%
V3
87.50%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 2.000s 45.505us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 124.828us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 122.079us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 249.384us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.558us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 10016.329us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 122.079us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 19.558us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 12.000s 1687.075us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 7.000s 222.727us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 14.000s 2442.962us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 231.000s 26719.042us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 11.000s 4275.195us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 17.000s 4529.472us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 7.000s 2761.032us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 13.000s 1049.452us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 2.000s 169.951us 8 8 100.00
sram_ctrl_partial_access_b2b 375.000s 48328.127us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 28.369us 0 8 0.00
sram_ctrl_throughput_w_partial_write 2.000s 48.902us 0 8 0.00
sram_ctrl_throughput_w_readback 2.000s 32.875us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 13.000s 8844.925us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 45.950us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 60.000s 11656.673us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 13.473us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 7.000s 1720.954us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 7.000s 1720.954us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 124.828us 1 1 100.00
sram_ctrl_csr_rw 2.000s 122.079us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 19.558us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 41.166us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 124.828us 1 1 100.00
sram_ctrl_csr_rw 2.000s 122.079us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 19.558us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 41.166us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 7.000s 2373.579us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 712.630us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 994.833us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 712.630us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 994.833us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 13.000s 8844.925us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 13.000s 8844.925us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 122.079us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 13.000s 1049.452us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 13.000s 1049.452us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 13.000s 1049.452us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 7.000s 2761.032us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 90.528us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 7.000s 2373.579us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 145.162us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 2.000s 45.505us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 2.000s 45.505us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 13.000s 1049.452us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 712.630us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 7.000s 2761.032us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 712.630us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 712.630us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 2.000s 45.505us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 712.630us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 8 87.50
sram_ctrl_stress_all_with_rand_reset 74.000s 3265.991us 7 8 87.50

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 3966517254842587791320091607381001470629467693398571666272108267510985610529 86
UVM_INFO @ 28368763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 86752198094313116745689477480274385820979839661431206786122643463738518919597 86
UVM_INFO @ 48901550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 103469615699042300826216788498986937542163660729075942171919741677574155074690 86
UVM_INFO @ 29226298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 39877678683800963254123214672224790844346249647729944436248025741087855586839 86
UVM_INFO @ 53846294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 62799423948399113972350708918940737548401551277394498949752363535800640131484 86
UVM_INFO @ 23442344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 13104766270111062780628668375652315193521768209392627702095837602721536527037 86
UVM_INFO @ 111046282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 32436026093293120481057934493986321065956294020496560415236301549558976120862 86
UVM_INFO @ 29795304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 47752714728182857953361968372514628853158500683129600352775054081890586755185 86
UVM_INFO @ 26251796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 53010056140532966630326876022621757106354712044755760698164667305225549127922 86
UVM_INFO @ 50440939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 55551979635311824244655795736760615129936404552833828396677682121371139084132 86
UVM_INFO @ 126462091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 33765277309385005027789553290507334667175698328745440639045731098093561036423 86
UVM_INFO @ 144901410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 108273121818001053573922810468698333250894993065610088226626329879529628622195 86
UVM_INFO @ 67252533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 112237532928234631409388579026599900417139204421557092119923669104691880579852 86
UVM_INFO @ 245072241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 112366264881259213541608271124212869066873505420454910683147871808530329593341 86
UVM_INFO @ 241845020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 108888024657401696483865631196593722428414881731414901591084656913524996525886 86
UVM_INFO @ 69412813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 9747254062533731545646669553675742763986798281020163658866391506425269790269 86
UVM_INFO @ 34103880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 72675355215113543963925866275498441571730378173114972897404260907252629742970 86
UVM_INFO @ 32874842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 113461660966979961992948926215044035940610425400521999602312746658459427085645 86
UVM_INFO @ 44804506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 94454462329260401323205677433792155038558056157934554766945260769946785640174 86
UVM_INFO @ 32323642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 71542203518615134257097032193720024173478731774586837244577956712693624128997 86
UVM_INFO @ 168700118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 86777246221643772888434585226675694671466283854648705210388728079269532023577 86
UVM_INFO @ 48663699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 53250692230917590460787438538529154055839011044639821037707026885079181611969 86
UVM_INFO @ 88568935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 85345596906231457549658607731162485138655237285915787376446866267064612150102 86
UVM_INFO @ 311527930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 46930896021979959002275977734969988547485111115068351392705540805266889316341 86
UVM_INFO @ 179132123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_stress_all_with_rand_reset 102193904241346353994362543261466953783770397532593880910332660954673003171636 115
UVM_INFO @ 209354136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 101164110285396368728933193942183339217547128017179659928635269320988357752672 85
UVM_INFO @ 10016329437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---