Simulation Results: dma

 
26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.95 %
  • code
  • 90.76 %
  • assert
  • 96.61 %
  • func
  • 79.49 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
93.55%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 8.000s 1285.739us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 8.000s 1661.316us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 8.000s 519.202us 50 50 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 39.183us 1 1 100.00
csr_rw 5 5 100.00
dma_csr_rw 2.000s 73.825us 5 5 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 18.000s 3830.810us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 5.000s 2449.255us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 39.844us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
dma_csr_rw 2.000s 73.825us 5 5 100.00
dma_csr_aliasing 5.000s 2449.255us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 81.000s 4925.140us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 834.000s 55960.983us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 1177.000s 288775.796us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 1177.000s 288775.796us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 834.000s 55960.983us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 1103.000s 199628.212us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 1177.000s 288775.796us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 9.000s 455.978us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 223.000s 56255.323us 3 3 100.00
alert_test 10 10 100.00
dma_alert_test 2.000s 30.700us 10 10 100.00
intr_test 10 10 100.00
dma_intr_test 2.000s 15.671us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
dma_tl_errors 4.000s 198.043us 25 25 100.00
tl_d_illegal_access 25 25 100.00
dma_tl_errors 4.000s 198.043us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
dma_csr_hw_reset 2.000s 39.183us 1 1 100.00
dma_csr_rw 2.000s 73.825us 5 5 100.00
dma_csr_aliasing 5.000s 2449.255us 1 1 100.00
dma_same_csr_outstanding 3.000s 114.291us 5 5 100.00
tl_d_partial_access 12 12 100.00
dma_csr_hw_reset 2.000s 39.183us 1 1 100.00
dma_csr_rw 2.000s 73.825us 5 5 100.00
dma_csr_aliasing 5.000s 2449.255us 1 1 100.00
dma_same_csr_outstanding 3.000s 114.291us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 29.000s 242.500us 5 5 100.00
dma_generic_stress 1103.000s 199628.212us 5 5 100.00
dma_handshake_stress 1177.000s 288775.796us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 11.000s 1795.772us 15 15 100.00
tl_intg_err 30 30 100.00
dma_tl_intg_err 5.000s 860.833us 25 25 100.00
dma_sec_cm 2.000s 30.998us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 29 31 93.55
dma_short_transfer 185.000s 200000.000us 24 25 96.00
dma_longer_transfer 182.000s 9457.852us 5 5 100.00
dma_stress_all_with_rand_reset 8.000s 374.131us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 61488709271281445571878746402004625703016559268988112304446406136733796104965 97
UVM_INFO @ 374130768ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ *ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of *ps hit, indicating a probable testbench issue 1 test run
dma_short_transfer 41537780865375254541284193604615607558959463059858937520640620948944698820912 2477
UVM_INFO @ 200000000000ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---