Simulation Results: sram_ctrl/main

 
26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.76 %
  • code
  • 95.77 %
  • assert
  • 98.10 %
  • func
  • 96.40 %
  • block
  • 96.17 %
  • line
  • 96.90 %
  • branch
  • 94.34 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 6.000s 691.592us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 19.848us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 1.000s 43.552us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 137.384us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 79.171us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 6.000s 360.262us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 1.000s 43.552us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 79.171us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 324.000s 183934.215us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 136.000s 30320.129us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 55.000s 24389.826us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 215.000s 5644.982us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 236.000s 174791.133us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 84.000s 48444.584us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 83.000s 28211.568us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 47.000s 6766.850us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 6.000s 729.013us 8 8 100.00
sram_ctrl_partial_access_b2b 381.000s 206965.551us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 7.000s 2748.365us 0 8 0.00
sram_ctrl_throughput_w_partial_write 9.000s 13195.932us 0 8 0.00
sram_ctrl_throughput_w_readback 7.000s 1340.636us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 19.000s 2947.535us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 5.000s 3351.863us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 785.000s 322389.407us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 14.779us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 307.337us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 307.337us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 19.848us 1 1 100.00
sram_ctrl_csr_rw 1.000s 43.552us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 79.171us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 16.667us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 19.848us 1 1 100.00
sram_ctrl_csr_rw 1.000s 43.552us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 79.171us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 16.667us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 44.000s 87947.713us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 3176.704us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 364.720us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 3176.704us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 364.720us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 19.000s 2947.535us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 19.000s 2947.535us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 1.000s 43.552us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 47.000s 6766.850us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 47.000s 6766.850us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 47.000s 6766.850us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 83.000s 28211.568us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 8.000s 4155.233us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 44.000s 87947.713us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 8.000s 4770.424us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 6.000s 691.592us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 6.000s 691.592us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 47.000s 6766.850us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 3176.704us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 83.000s 28211.568us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 3176.704us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 3176.704us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 6.000s 691.592us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 3176.704us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 45.000s 19180.138us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 37461380668206925583175049528866451996263910745519829583383139503661199878531 86
UVM_INFO @ 689127526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 53399262960494341040419024040533189638767000384654687364456906752931554015681 86
UVM_INFO @ 1384821247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 78543713116136611292820814661393430107091633866100983703492561107982288695109 86
UVM_INFO @ 2748365063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 94563511307217604749611837511364264428634009649098293389976738139978814312940 86
UVM_INFO @ 667867313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 36013634816419029027685646857855769477483454813553691380976416265934207348677 86
UVM_INFO @ 1393445640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 99363490166830481900596877804190659713582288911610193210026274216061837273452 86
UVM_INFO @ 2626862427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 44856493424533946287529208525867869557541362458835514455349347914242555361301 86
UVM_INFO @ 1297675236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 92493039742513272737048580166019929711834880187338713399070449890216694985981 86
UVM_INFO @ 13195931712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 99367586340729275114105758182004585440183353984644592602198355354928647099519 86
UVM_INFO @ 1407302198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 90129512807750718397529430629647392469808817264551298602346326591756758956822 86
UVM_INFO @ 9427396993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 18885484691991134335577820844638327858945394018473341881734543536797291296319 86
UVM_INFO @ 2662375489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 33530072839018748966841375134816702334864515797402081423330142714802946431969 86
UVM_INFO @ 5473927049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 80693707111673172904845637018560860535835112177526838539061555032916592394484 86
UVM_INFO @ 868330849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 69414994258327076042392722486851024969086677085020831702621227088428279350570 86
UVM_INFO @ 689438721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 50946235091455969172330617781073096929454554472116292847312146117163411603914 86
UVM_INFO @ 2643339572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 36312139168426565856052208649442296952824670096263595266143546265045139376023 86
UVM_INFO @ 2871025534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 4541792082987899208984503754116203424879529676601032991275927190103631029573 86
UVM_INFO @ 671097102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 87918792515305065189475707777483398006659848776264867745172936454791500502675 86
UVM_INFO @ 1355379536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 53516197107749803378915777744014706539954448298460373028101348292598819610284 86
UVM_INFO @ 709085102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 34127876650092439199282037558688119223537314824623195391888517327863787967491 86
UVM_INFO @ 2764397728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 91306425814125140623161569927157405454129541840143035696598816687273001612286 86
UVM_INFO @ 695012329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 20224070214050788741586878466024017553890221064966451919221486181416105081945 86
UVM_INFO @ 1340636000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 3484372842618082756551160618325568855189555100290649182630810389956793126901 86
UVM_INFO @ 2764174275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 18009576073279154163231386863119333165040112254883589454765493463160437989463 86
UVM_INFO @ 2772716774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---