Simulation Results: sram_ctrl/ret

 
03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.44 %
  • code
  • 82.43 %
  • assert
  • 98.08 %
  • func
  • 96.80 %
  • block
  • 93.90 %
  • line
  • 95.06 %
  • branch
  • 89.67 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
84.28%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 2.000s 164.057us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 22.926us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 69.323us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 219.628us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 43.663us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 35.889us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 69.323us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 43.663us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 15.000s 2833.038us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 7.000s 650.378us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 13.000s 362.477us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 199.000s 12919.159us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 10.000s 1924.446us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 17.000s 2549.610us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 7.000s 741.596us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 12.000s 2558.855us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 2.000s 91.976us 8 8 100.00
sram_ctrl_partial_access_b2b 201.000s 30404.342us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 99.791us 0 8 0.00
sram_ctrl_throughput_w_partial_write 3.000s 173.604us 0 8 0.00
sram_ctrl_throughput_w_readback 2.000s 121.311us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 13.000s 3472.417us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 47.432us 8 8 100.00
stress_all 7 8 87.50
sram_ctrl_stress_all 53.000s 3294.017us 7 8 87.50
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 18.156us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 729.209us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 729.209us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 22.926us 1 1 100.00
sram_ctrl_csr_rw 2.000s 69.323us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 43.663us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 19.307us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 22.926us 1 1 100.00
sram_ctrl_csr_rw 2.000s 69.323us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 43.663us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 19.307us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 1536.283us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 727.876us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 298.228us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 727.876us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 298.228us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 13.000s 3472.417us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 13.000s 3472.417us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 69.323us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 12.000s 2558.855us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 12.000s 2558.855us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 12.000s 2558.855us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 7.000s 741.596us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 68.591us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 1536.283us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 105.544us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 2.000s 164.057us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 2.000s 164.057us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 12.000s 2558.855us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 727.876us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 7.000s 741.596us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 727.876us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 727.876us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 2.000s 164.057us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 727.876us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 58.000s 1221.621us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 114659844431444452965658265965846976243428779776102287036532807645298316712266 86
UVM_INFO @ 99790829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 89167501294431776713353614139073342437755106599391564408173938187129761005249 86
UVM_INFO @ 27277297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 1034471207054838846920802069330426173750374492799517779294598120637047395409 86
UVM_INFO @ 29911844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 8640870023703422916816836378007034916318162542951326864226050197409783193262 86
UVM_INFO @ 92251442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 30870359764031713844742671576129553790626490362000551930168032120185046108223 86
UVM_INFO @ 26542165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 81292236237714643029890159998317393857199221448411342512940609835974152945157 86
UVM_INFO @ 497197159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 109935628656219999928948085877758946708374660813346897311449698491905025663440 86
UVM_INFO @ 51033195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 900068496467313233252935684174163545560005674660553295592544501967193209083 86
UVM_INFO @ 173604371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 48074854693603492885684239130421919676300819875483934144623034778606752432216 86
UVM_INFO @ 106298983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 40713707624661005271179123296976785493333024255136967988605289438018330215734 86
UVM_INFO @ 115723600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 42805058524413591413572400000374827694680576611258236213378916528303561567880 86
UVM_INFO @ 25694092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 107683424781960593472700825392036954272618519206785652458799713470460461283752 86
UVM_INFO @ 34173608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 34503157441952179824284898105050287087652683494081658007887394273534817725499 86
UVM_INFO @ 108360299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 39467885166777133244716307315271956879506270189985091040380487658773046167894 86
UVM_INFO @ 140827843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 23826032973316134379581075814766021109856313954521320028804434769466438141927 86
UVM_INFO @ 490513846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 31008671645756856037975199921164059800670484434075362450757874356453730126059 86
UVM_INFO @ 132881653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 42338296978675498019120848737820446459765636891458199568204198016496769212235 86
UVM_INFO @ 117547840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 59671971851069156932348172677782928115290758059474369188948649151166784889299 86
UVM_INFO @ 92775606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 94956773730907370826234390163998418720546051794494215611265265312356650920319 86
UVM_INFO @ 121310901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 30845251496550593043640998782833589960539631387443492896164264490780914573709 86
UVM_INFO @ 44635522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 88026410118387097152792069017565104852297533065270035431492300449222460145039 86
UVM_INFO @ 63162342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 96463570903140610661447817694948045351678157823340161302015539660614451803295 86
UVM_INFO @ 22879966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 107867636585630265623092130085155470477609395753036767802655090679377290520982 86
UVM_INFO @ 56353489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 43849841021447405031546248752987573628742879771687666566574624444006155204917 86
UVM_INFO @ 60292042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mem_model.sv:49) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch 1 test run
sram_ctrl_stress_all 82344605742979318951577241070259300725463007253725819081964856706876918096838 197
UVM_INFO @ 2607073319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---