Simulation Results

Simulation Results: otbn

10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.86 %

code
87.04 %

assert
97.54 %

func
100.00 %

block
99.38 %

line
99.56 %

branch
95.47 %

toggle
85.51 %

FSM
67.61 %

Validation stages

V1		99.14%
V2		98.77%
V2S		96.35%
V3		40.00%
unmapped		100.00%

115/116 passed

99.14 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	otbn_smoke	13.000s	56.974us	1	1	100.00
single_binary				99	100	99.00
	otbn_single	131.000s	717.699us	99	100	99.00
csr_hw_reset				1	1	100.00
	otbn_csr_hw_reset	7.000s	119.847us	1	1	100.00
csr_rw				5	5	100.00
	otbn_csr_rw	7.000s	15.475us	5	5	100.00
csr_bit_bash				1	1	100.00
	otbn_csr_bit_bash	8.000s	54.595us	1	1	100.00
csr_aliasing				1	1	100.00
	otbn_csr_aliasing	7.000s	52.471us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	otbn_csr_mem_rw_with_rand_reset	10.000s	287.833us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otbn_csr_rw	7.000s	15.475us	5	5	100.00
	otbn_csr_aliasing	7.000s	52.471us	1	1	100.00
mem_walk				1	1	100.00
	otbn_mem_walk	70.000s	2818.613us	1	1	100.00
mem_partial_access				1	1	100.00
	otbn_mem_partial_access	29.000s	644.498us	1	1	100.00

161/163 passed

98.77 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reset_recovery				10	10	100.00
	otbn_reset	49.000s	146.849us	10	10	100.00
multi_error				1	1	100.00
	otbn_multi_err	82.000s	284.021us	1	1	100.00
back_to_back				10	10	100.00
	otbn_multi	151.000s	1415.612us	10	10	100.00
stress_all				10	10	100.00
	otbn_stress_all	1384.000s	3824.788us	10	10	100.00
lc_escalation				59	60	98.33
	otbn_escalate	91.000s	341.848us	59	60	98.33
zero_state_err_urnd				4	5	80.00
	otbn_zero_state_err_urnd	7.000s	34.381us	4	5	80.00
sw_errs_fatal_chk				10	10	100.00
	otbn_sw_errs_fatal_chk	25.000s	46.656us	10	10	100.00
alert_test				10	10	100.00
	otbn_alert_test	9.000s	16.517us	10	10	100.00
intr_test				10	10	100.00
	otbn_intr_test	6.000s	16.086us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otbn_tl_errors	9.000s	83.912us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otbn_tl_errors	9.000s	83.912us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otbn_csr_hw_reset	7.000s	119.847us	1	1	100.00
	otbn_csr_rw	7.000s	15.475us	5	5	100.00
	otbn_csr_aliasing	7.000s	52.471us	1	1	100.00
	otbn_same_csr_outstanding	6.000s	46.625us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otbn_csr_hw_reset	7.000s	119.847us	1	1	100.00
	otbn_csr_rw	7.000s	15.475us	5	5	100.00
	otbn_csr_aliasing	7.000s	52.471us	1	1	100.00
	otbn_same_csr_outstanding	6.000s	46.625us	5	5	100.00

V2S

317/329 passed

96.35 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
mem_integrity				25	25	100.00
	otbn_imem_err	10.000s	169.140us	10	10	100.00
	otbn_dmem_err	18.000s	36.545us	15	15	100.00
internal_integrity				16	17	94.12
	otbn_alu_bignum_mod_err	16.000s	142.495us	4	5	80.00
	otbn_controller_ispr_rdata_err	12.000s	59.642us	5	5	100.00
	otbn_mac_bignum_acc_err	26.000s	71.562us	5	5	100.00
	otbn_urnd_err	8.000s	19.137us	2	2	100.00
illegal_bus_access				5	5	100.00
	otbn_illegal_mem_acc	8.000s	16.108us	5	5	100.00
otbn_mem_gnt_acc_err				1	2	50.00
	otbn_mem_gnt_acc_err	7.000s	24.041us	1	2	50.00
otbn_non_sec_partial_wipe				9	10	90.00
	otbn_partial_wipe	9.000s	90.821us	9	10	90.00
tl_intg_err				27	30	90.00
	otbn_sec_cm	218.000s	1779.944us	2	5	40.00
	otbn_tl_intg_err	66.000s	378.686us	25	25	100.00
passthru_mem_tl_intg_err				5	5	100.00
	otbn_passthru_mem_tl_intg_err	54.000s	831.526us	5	5	100.00
prim_fsm_check				2	5	40.00
	otbn_sec_cm	218.000s	1779.944us	2	5	40.00
prim_count_check				2	5	40.00
	otbn_sec_cm	218.000s	1779.944us	2	5	40.00
sec_cm_mem_scramble				1	1	100.00
	otbn_smoke	13.000s	56.974us	1	1	100.00
sec_cm_data_mem_integrity				15	15	100.00
	otbn_dmem_err	18.000s	36.545us	15	15	100.00
sec_cm_instruction_mem_integrity				10	10	100.00
	otbn_imem_err	10.000s	169.140us	10	10	100.00
sec_cm_bus_integrity				25	25	100.00
	otbn_tl_intg_err	66.000s	378.686us	25	25	100.00
sec_cm_controller_fsm_global_esc				59	60	98.33
	otbn_escalate	91.000s	341.848us	59	60	98.33
sec_cm_controller_fsm_local_esc				36	40	90.00
	otbn_imem_err	10.000s	169.140us	10	10	100.00
	otbn_dmem_err	18.000s	36.545us	15	15	100.00
	otbn_zero_state_err_urnd	7.000s	34.381us	4	5	80.00
	otbn_illegal_mem_acc	8.000s	16.108us	5	5	100.00
	otbn_sec_cm	218.000s	1779.944us	2	5	40.00
sec_cm_controller_fsm_sparse				2	5	40.00
	otbn_sec_cm	218.000s	1779.944us	2	5	40.00
sec_cm_scramble_key_sideload				99	100	99.00
	otbn_single	131.000s	717.699us	99	100	99.00
sec_cm_scramble_ctrl_fsm_local_esc				36	40	90.00
	otbn_imem_err	10.000s	169.140us	10	10	100.00
	otbn_dmem_err	18.000s	36.545us	15	15	100.00
	otbn_zero_state_err_urnd	7.000s	34.381us	4	5	80.00
	otbn_illegal_mem_acc	8.000s	16.108us	5	5	100.00
	otbn_sec_cm	218.000s	1779.944us	2	5	40.00
sec_cm_scramble_ctrl_fsm_sparse				2	5	40.00
	otbn_sec_cm	218.000s	1779.944us	2	5	40.00
sec_cm_start_stop_ctrl_fsm_global_esc				59	60	98.33
	otbn_escalate	91.000s	341.848us	59	60	98.33
sec_cm_start_stop_ctrl_fsm_local_esc				36	40	90.00
	otbn_imem_err	10.000s	169.140us	10	10	100.00
	otbn_dmem_err	18.000s	36.545us	15	15	100.00
	otbn_zero_state_err_urnd	7.000s	34.381us	4	5	80.00
	otbn_illegal_mem_acc	8.000s	16.108us	5	5	100.00
	otbn_sec_cm	218.000s	1779.944us	2	5	40.00
sec_cm_start_stop_ctrl_fsm_sparse				2	5	40.00
	otbn_sec_cm	218.000s	1779.944us	2	5	40.00
sec_cm_data_reg_sw_sca				99	100	99.00
	otbn_single	131.000s	717.699us	99	100	99.00
sec_cm_ctrl_redun				12	12	100.00
	otbn_ctrl_redun	12.000s	36.556us	12	12	100.00
sec_cm_pc_ctrl_flow_redun				5	5	100.00
	otbn_pc_ctrl_flow_redun	10.000s	29.161us	5	5	100.00
sec_cm_rnd_bus_consistency				5	5	100.00
	otbn_rnd_sec_cm	57.000s	234.208us	5	5	100.00
sec_cm_rnd_rng_digest				5	5	100.00
	otbn_rnd_sec_cm	57.000s	234.208us	5	5	100.00
sec_cm_rf_base_data_reg_sw_integrity				10	10	100.00
	otbn_rf_base_intg_err	15.000s	63.360us	10	10	100.00
sec_cm_rf_base_data_reg_sw_glitch_detect				2	5	40.00
	otbn_sec_cm	218.000s	1779.944us	2	5	40.00
sec_cm_stack_wr_ptr_ctr_redun				2	5	40.00
	otbn_sec_cm	218.000s	1779.944us	2	5	40.00
sec_cm_rf_bignum_data_reg_sw_integrity				7	10	70.00
	otbn_rf_bignum_intg_err	12.000s	48.496us	7	10	70.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect				2	5	40.00
	otbn_sec_cm	218.000s	1779.944us	2	5	40.00
sec_cm_loop_stack_ctr_redun				2	5	40.00
	otbn_sec_cm	218.000s	1779.944us	2	5	40.00
sec_cm_loop_stack_addr_integrity				5	5	100.00
	otbn_stack_addr_integ_chk	11.000s	19.687us	5	5	100.00
sec_cm_call_stack_addr_integrity				5	5	100.00
	otbn_stack_addr_integ_chk	11.000s	19.687us	5	5	100.00
sec_cm_start_stop_ctrl_state_consistency				7	7	100.00
	otbn_sec_wipe_err	26.000s	56.232us	7	7	100.00
sec_cm_data_mem_sec_wipe				99	100	99.00
	otbn_single	131.000s	717.699us	99	100	99.00
sec_cm_instruction_mem_sec_wipe				99	100	99.00
	otbn_single	131.000s	717.699us	99	100	99.00
sec_cm_data_reg_sw_sec_wipe				99	100	99.00
	otbn_single	131.000s	717.699us	99	100	99.00
sec_cm_write_mem_integrity				10	10	100.00
	otbn_multi	151.000s	1415.612us	10	10	100.00
sec_cm_ctrl_flow_count				99	100	99.00
	otbn_single	131.000s	717.699us	99	100	99.00
sec_cm_ctrl_flow_sca				99	100	99.00
	otbn_single	131.000s	717.699us	99	100	99.00
sec_cm_data_mem_sw_noaccess				5	5	100.00
	otbn_sw_no_acc	21.000s	52.300us	5	5	100.00
sec_cm_key_sideload				99	100	99.00
	otbn_single	131.000s	717.699us	99	100	99.00
sec_cm_tlul_fifo_ctr_redun				2	5	40.00
	otbn_sec_cm	218.000s	1779.944us	2	5	40.00

4/10 passed

40.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				4	10	40.00
	otbn_stress_all_with_rand_reset	407.000s	9726.800us	4	10	40.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	otbn_smoke_vectorized	10.000s	26.198us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error				4 test runs
	otbn_alu_bignum_mod_err	80416593851037395759102209629711613626247852481167295053306738814607728930110	141	UVM_INFO @ 73987025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_rf_bignum_intg_err	89696981402362810116454919874650837287073388159536517668024038624836792158299	114	UVM_INFO @ 48496315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_rf_bignum_intg_err	87138906630885659864233618481944549778494854035254520112462563509118644947007	121	UVM_INFO @ 21802991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_rf_bignum_intg_err	112628621636542106489350233277103193339509237291229542901313829038666952185115	116	UVM_INFO @ 268199540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				4 test runs
	otbn_stress_all_with_rand_reset	75798048001279753686292835429867814291641375655024098597736023161220215134359	215	UVM_INFO @ 606628466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	53448762003292106418751877788981810923966673367840015493494184128771390186605	255	UVM_INFO @ 1089773519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	105693083598105091872010278624005677741931181808988580614518203370810436096070	262	UVM_INFO @ 895773614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	16975413091976823249804430009680582330514247696106338381896655289626568810452	170	UVM_INFO @ 2256374430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed				3 test runs
	otbn_sec_cm	8718843320621505757714336849045535806658742271555876420163191902519717668092	140	UVM_ERROR @ 75459768 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 75459768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_sec_cm	85972243217821836708611807451872131988323405884119985706660214729500765747603	104	UVM_ERROR @ 68089019 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 68089019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_sec_cm	75550109732037178143164284760583609492787601480712114820101838779322012932947	85	UVM_ERROR @ 1036905 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 1036905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	otbn_mem_gnt_acc_err	83319988025619840144415376458765500774408426948635636975337979791975097513107	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
	otbn_single	68506859702434987536327364887357151714371439232622452896114875481947771610935	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_/otbn_idle_checker.sv,161): Assertion IdleIfLockedAndNotRotatingKeys_A has failed (* cycles, starting * PS)				1 test run
	otbn_partial_wipe	111989135649285016115636449600578583368039777085354278023837575310651970424144	123	UVM_ERROR @ 26730923 ps: (otbn_idle_checker.sv:161) [ASSERT FAILED] IdleIfLockedAndNotRotatingKeys_A UVM_INFO @ 26730923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)				1 test run
	otbn_stress_all_with_rand_reset	36690625615618796017154901203092015034052707999824582394733395074218013554218	222	UVM_INFO @ 484879894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed				1 test run
	otbn_zero_state_err_urnd	19826490084770272502345957106228838928278429246957493929562365322689703720429	107	UVM_ERROR @ 33754958 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 33754958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)				1 test run
	otbn_stress_all_with_rand_reset	90735898443621006873847885355045503251900175684417933871896582050298544145915	154	UVM_INFO @ 62885375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [] vs [*]) value for register otbn_reg_block.status				1 test run
	otbn_escalate	70393049093676076928431470374090169429835314758178962806814594198043767807159	106	UVM_INFO @ 4851883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---