Simulation Results: rom_ctrl/32kb

 
10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.91 %
  • code
  • 94.00 %
  • assert
  • 97.67 %
  • func
  • 99.06 %
  • block
  • 96.76 %
  • line
  • 97.24 %
  • branch
  • 94.09 %
  • toggle
  • 84.66 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.77%
V2S
93.22%
V3
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 5.000s 173.298us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.000s 131.109us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 4.000s 127.725us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 290.818us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 768.662us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.000s 175.950us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 4.000s 127.725us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 768.662us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 130.447us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.000s 606.735us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 4.000s 125.912us 0 2 0.00
stress_all 19 20 95.00
rom_ctrl_stress_all 18.000s 590.654us 19 20 95.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 7.000s 225.575us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 5.000s 1090.917us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 9.000s 1798.082us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 9.000s 1798.082us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.000s 131.109us 1 1 100.00
rom_ctrl_csr_rw 4.000s 127.725us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 768.662us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 385.101us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.000s 131.109us 1 1 100.00
rom_ctrl_csr_rw 4.000s 127.725us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 768.662us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 385.101us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 12394.850us 16 20 80.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.000s 1659.247us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 147.000s 1619.606us 5 5 100.00
rom_ctrl_tl_intg_err 42.000s 464.512us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 147.000s 1619.606us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 147.000s 1619.606us 5 5 100.00
sec_cm_checker_ctr_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 12394.850us 16 20 80.00
sec_cm_checker_ctrl_flow_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 12394.850us 16 20 80.00
sec_cm_checker_fsm_local_esc 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 12394.850us 16 20 80.00
sec_cm_compare_ctrl_flow_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 12394.850us 16 20 80.00
sec_cm_compare_ctr_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 12394.850us 16 20 80.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 147.000s 1619.606us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 147.000s 1619.606us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 5.000s 173.298us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 5.000s 173.298us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 5.000s 173.298us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 42.000s 464.512us 25 25 100.00
sec_cm_bus_local_esc 18 22 81.82
rom_ctrl_corrupt_sig_fatal_chk 68.000s 12394.850us 16 20 80.00
rom_ctrl_kmac_err_chk 7.000s 225.575us 2 2 100.00
sec_cm_mux_mubi 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 12394.850us 16 20 80.00
sec_cm_mux_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 12394.850us 16 20 80.00
sec_cm_ctrl_redun 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 12394.850us 16 20 80.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.000s 1659.247us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 147.000s 1619.606us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 15 20 75.00
rom_ctrl_stress_all_with_rand_reset 120.000s 5375.597us 15 20 75.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 4 test runs
rom_ctrl_corrupt_sig_fatal_chk 71623037178895131226825251655308782658747116122287501075977835048630585712853 89
UVM_INFO @ 1518674009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 49426595290342100856268283082224247767217792809959822897362483439827630529603 99
UVM_INFO @ 2968216711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 44817861358216142882212048042026961145439469098313848036896739082581626334436 97
UVM_INFO @ 3429250785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 71513229568759615213032343845371866497169500248976390374693809889963321324437 87
UVM_INFO @ 412579048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 4 test runs
rom_ctrl_stress_all 37796357475795558321402854374118098117058171787110376094601889219598359378050 87
UVM_INFO @ 260321859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 12399125913620875930948001107091454740558686326035362008922549555328757397631 91
UVM_INFO @ 973809105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 109669256229568168352930566218907397654788689437952455682081162658301046750686 91
UVM_INFO @ 541052273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 84278203243344056798617907564615525117123383883831753502638447950456852639435 97
UVM_INFO @ 1191685401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 80974323749014361673527560469360542334894912989417740711580791731562103534546 88
UVM_INFO @ 363088013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 27660769862093713106047535115810422210756322666584008319664877725981405946028 88
UVM_INFO @ 125911784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:235) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 2 test runs
rom_ctrl_stress_all_with_rand_reset 69562700959799460778924651293305435684904248447025800987402443488588194788106 96
UVM_INFO @ 271797522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 22749966737031806677366495166337577044315766294285257609456478821798439667218 126
UVM_INFO @ 1172905878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---