Simulation Results: sram_ctrl/ret

 
17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.46 %
  • code
  • 82.51 %
  • assert
  • 98.08 %
  • func
  • 96.80 %
  • block
  • 94.03 %
  • line
  • 95.21 %
  • branch
  • 89.83 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 3.000s 292.136us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 22.098us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 1.000s 14.306us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 4.000s 378.980us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 44.577us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 79.343us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 1.000s 14.306us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 44.577us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 13.000s 1138.647us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 6.000s 973.054us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 17.000s 994.230us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 252.000s 4434.349us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 10.000s 1150.087us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 24.000s 2814.656us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 9.000s 2829.576us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 13.000s 1523.888us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 2.000s 91.199us 8 8 100.00
sram_ctrl_partial_access_b2b 367.000s 233061.332us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 26.276us 0 8 0.00
sram_ctrl_throughput_w_partial_write 2.000s 106.749us 0 8 0.00
sram_ctrl_throughput_w_readback 2.000s 287.181us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 15.000s 2294.540us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 75.681us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 57.000s 8345.834us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 14.497us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 562.928us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 562.928us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 22.098us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.306us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 44.577us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 41.355us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 22.098us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.306us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 44.577us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 41.355us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 1616.692us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 4.000s 1980.994us 5 5 100.00
sram_ctrl_tl_intg_err 3.000s 204.523us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 4.000s 1980.994us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 3.000s 204.523us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 15.000s 2294.540us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 15.000s 2294.540us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 1.000s 14.306us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 13.000s 1523.888us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 13.000s 1523.888us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 13.000s 1523.888us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 9.000s 2829.576us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 78.499us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 1616.692us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 96.926us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 292.136us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 292.136us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 13.000s 1523.888us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 4.000s 1980.994us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 9.000s 2829.576us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 4.000s 1980.994us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 1980.994us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 3.000s 292.136us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 1980.994us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 79.000s 1884.292us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 43775236962493822754572857438261817270464988261490350685833255425625098376901 86
UVM_INFO @ 26275939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 110338855950471800362707451332701222897602716956785095783474225834588302293157 86
UVM_INFO @ 106748807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 57939536229977297251249756578345658314271609709868186150438521954957809650463 86
UVM_INFO @ 25410252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 48369034170310275641157146093005018761369586046367959961832834153534811544530 86
UVM_INFO @ 38098123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 97552812737398828817789955034200760794981756155190051996052852933885264156035 86
UVM_INFO @ 33183341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 82929225011145828697738298894855799198084819348990017190140099632809273334248 86
UVM_INFO @ 63878790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 90349645138205447051395346796915573388125174913396846346809394093379636403930 86
UVM_INFO @ 52048143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 40812166736323768157225409970516440349264731223412313562883321288336302036304 86
UVM_INFO @ 44874631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 109047203224428612213901184479570301232891082113074996341513947074779670722752 86
UVM_INFO @ 53705330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 100277197608080202600097626367854578167360655371540180000075064945200076534102 86
UVM_INFO @ 25467856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 51645305744994177986031119980430807236199607579956899330885123767343778870685 86
UVM_INFO @ 278324703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 5687938309094522880875958138544127597573633290586017121075113420542980122599 86
UVM_INFO @ 50219675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 70082224286046135357374466446600487777867062191497310202725839697906669970677 86
UVM_INFO @ 135765627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 107104497386109838517128508326077632597712044100050680876956470821941425710242 86
UVM_INFO @ 55811251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 54619596004728091088804639081792384576734232290163714928510485023399005000089 86
UVM_INFO @ 77618896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 50877282856798703469217593492716976727973385867720074695949855487706751029070 86
UVM_INFO @ 130784176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 16784185671998884126954735932716960404971786372277671583937632437788042682673 86
UVM_INFO @ 287180860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 6392745587893595523037440739138811239226030248822579683203687651667455283542 86
UVM_INFO @ 107787756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 81686108329048619748766674488730906172401026182145396209474915678988596261782 86
UVM_INFO @ 36855386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 12558323279102111498189863858329823046963920947087509490613685102231042670196 86
UVM_INFO @ 219066515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 25821984350356610454386043358765196426208212202374317257366030735127451953647 86
UVM_INFO @ 121994311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 8856727396384594161559186587881874842131271190041015974285732362422754077083 86
UVM_INFO @ 49389055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 104418721559801827297063840756614689266886200809293500949220096030561260337778 86
UVM_INFO @ 57010170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 91069744535993960938153597774070752239084642538478136317119175463793613197053 86
UVM_INFO @ 120373080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---