| V1 |
|
100.00% |
| V2 |
|
93.63% |
| V2S |
|
90.00% |
| V3 |
|
50.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 40 | 40 | 100.00 | |||
| gpio_smoke | 2.340s | 101.875us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 2.230s | 193.811us | 10 | 10 | 100.00 | |
| gpio_smoke_en_cdc_prim | 2.390s | 98.083us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 2.120s | 1794.843us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.990s | 24.058us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| gpio_csr_rw | 1.130s | 27.147us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 7.150s | 837.285us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 2.290s | 105.429us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.820s | 93.271us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| gpio_csr_rw | 1.130s | 27.147us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 2.290s | 105.429us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 20 | 20 | 100.00 | |||
| gpio_random_dout_din | 2.270s | 308.985us | 10 | 10 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.800s | 61.711us | 10 | 10 | 100.00 | |
| out_in_regs_read_write | 10 | 10 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 1.460s | 189.057us | 10 | 10 | 100.00 | |
| gpio_interrupt_programming | 10 | 10 | 100.00 | |||
| gpio_intr_rand_pgm | 2.220s | 57.664us | 10 | 10 | 100.00 | |
| random_interrupt_trigger | 10 | 10 | 100.00 | |||
| gpio_rand_intr_trigger | 5.170s | 380.051us | 10 | 10 | 100.00 | |
| interrupt_and_noise_filter | 10 | 10 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 3.900s | 970.449us | 10 | 10 | 100.00 | |
| noise_filter_stress | 10 | 10 | 100.00 | |||
| gpio_filter_stress | 24.650s | 696.426us | 10 | 10 | 100.00 | |
| regs_long_reads_and_writes | 10 | 10 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 8.430s | 2401.712us | 10 | 10 | 100.00 | |
| full_random | 10 | 10 | 100.00 | |||
| gpio_full_random | 1.610s | 470.885us | 10 | 10 | 100.00 | |
| stress_all | 1 | 10 | 10.00 | |||
| gpio_stress_all | 82.220s | 3068.115us | 1 | 10 | 10.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| gpio_alert_test | 0.930s | 14.284us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| gpio_intr_test | 0.960s | 18.354us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 4.580s | 987.825us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 4.580s | 987.825us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 11 | 12 | 91.67 | |||
| gpio_csr_rw | 1.130s | 27.147us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.750s | 79.365us | 4 | 5 | 80.00 | |
| gpio_csr_aliasing | 2.290s | 105.429us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.990s | 24.058us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 11 | 12 | 91.67 | |||
| gpio_csr_rw | 1.130s | 27.147us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.750s | 79.365us | 4 | 5 | 80.00 | |
| gpio_csr_aliasing | 2.290s | 105.429us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.990s | 24.058us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 27 | 30 | 90.00 | |||
| gpio_tl_intg_err | 3.580s | 774.700us | 22 | 25 | 88.00 | |
| gpio_sec_cm | 1.350s | 213.250us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 22 | 25 | 88.00 | |||
| gpio_tl_intg_err | 3.580s | 774.700us | 22 | 25 | 88.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 10 | 10 | 100.00 | |||
| gpio_rand_straps | 0.920s | 13.968us | 10 | 10 | 100.00 | |
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 19.090s | 613.972us | 0 | 10 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 50 | 50 | 100.00 | |||
| gpio_inp_prd_cnt | 0.950s | 39.914us | 50 | 50 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 9 test runs | |||
| gpio_stress_all | 71461685901330913921196783215771382092939806596564175180481402660647109516837 | 975 |
UVM_INFO @ 5865431120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 99881181307136954485523946570869402192523860538727160046918956250192841829846 | 78 |
UVM_INFO @ 164433867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 36099242639280245938159965784402547149006666551954684724104318598256204742025 | 78 |
UVM_INFO @ 598883245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 37737936377761050050733377316353550528799211173193774182437593383067936346445 | 373 |
UVM_INFO @ 7423740264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 89364917817546691791250726736913805400774732067516426812950433861585241364991 | 127 |
UVM_INFO @ 2997617112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 40609265539261239877646471696095680643342755171072061865898072507497790771101 | 488 |
UVM_INFO @ 3698584176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 4577854507669980602276981141577903930911301525829920827680429978966510235982 | 426 |
UVM_INFO @ 2274117294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 72699225736154389594334505089107862230114198327967102429617171175766120177364 | 76 |
UVM_INFO @ 13146243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 46808857733500889973311934517548681734094177363631598512621530522576444462943 | 1073 |
UVM_INFO @ 3079259492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done) | 7 test runs | |||
| gpio_stress_all_with_rand_reset | 79964591093580769409773016188018698547149382099802695324398258819252265944744 | 129 |
UVM_INFO @ 556132019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 13646052192769871068417803567025876884953192697237328240923916038207889426412 | 84 |
UVM_INFO @ 1286546270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 89365067404077405532530741016970040890635372065839172783610625498929826868141 | 301 |
UVM_INFO @ 4042533645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 82398979541182256149626166557817163933516056061528437917806815054781278327905 | 354 |
UVM_INFO @ 4230601499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 36207625585246088471420777076031365254398063548480448144093737891333929883812 | 80 |
UVM_INFO @ 26286248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 23410775754177840766788110073184022064270238979971877446904178608823373122448 | 254 |
UVM_INFO @ 613972378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 87156514144008254965727091197234434639072111928600021001615616363345992642563 | 80 |
UVM_INFO @ 10224017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 3 test runs | |||
| gpio_stress_all_with_rand_reset | 99847940196826505319944319535221508651219055703779666934665826295362883318969 | 78 |
UVM_INFO @ 4898162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 87110625928135963238518087156354240941738835204342204618585749817729172899529 | 80 |
UVM_INFO @ 549975495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 52862736575559099551599818364080552092971809108759638461007649573012175794093 | 78 |
UVM_INFO @ 134582856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_* reset value: * | 2 test runs | |||
| gpio_tl_intg_err | 23033243206624720688767666753223423280835575367608654538086562725236343848476 | 84 |
UVM_INFO @ 17170530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_tl_intg_err | 72806762910743940747862226081508901883444243541839744290316997533393598027115 | 284 |
UVM_INFO @ 169451098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:660) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 1 test run | |||
| gpio_same_csr_outstanding | 35256502000366758911775958519251063119411698546943979788215253103784613347906 | 78 |
UVM_INFO @ 18379861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_*.enable reset value: * | 1 test run | |||
| gpio_tl_intg_err | 73848612422151077617664458151639219848613951547656789840699993007474978191721 | 239 |
UVM_INFO @ 112432604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|