Simulation Results: rstmgr_cnsty_chk

 
07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.52 %
  • code
  • 95.05 %
  • assert
  • 100.00 %
  • line
  • 98.41 %
  • branch
  • 98.31 %
  • cond
  • 86.21 %
  • toggle
  • 100.00 %
  • FSM
  • 92.31 %
Validation stages
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
rstmgr_cnsty_chk_test 4.020s 9328.869us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *)) 2 test runs
rstmgr_cnsty_chk_test 111035026725970378287568313390325314239539951007585145774452288481759264948260 175
UVM_INFO @ 1816312467 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 1834392467 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 1852472467 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 1870552467 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
rstmgr_cnsty_chk_test 59159089268295499667991828849749401822368065973125504961726554000782396630046 175
UVM_INFO @ 1896456136 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 1915336136 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 1934216136 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 1953096136 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16