Simulation Results: uart

 
07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.09 %
  • code
  • 92.73 %
  • assert
  • 98.85 %
  • func
  • 90.69 %
  • block
  • 99.08 %
  • line
  • 99.52 %
  • branch
  • 98.34 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.23%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
uart_smoke 22.000s 6277.605us 10 10 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 2.000s 93.795us 1 1 100.00
csr_rw 5 5 100.00
uart_csr_rw 2.000s 12.470us 5 5 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 4.000s 1199.181us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 87.814us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 42.295us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
uart_csr_rw 2.000s 12.470us 5 5 100.00
uart_csr_aliasing 2.000s 87.814us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 10 10 100.00
uart_tx_rx 181.000s 113819.909us 10 10 100.00
parity 20 20 100.00
uart_smoke 22.000s 6277.605us 10 10 100.00
uart_tx_rx 181.000s 113819.909us 10 10 100.00
parity_error 20 20 100.00
uart_intr 774.000s 573530.426us 10 10 100.00
uart_rx_parity_err 91.000s 70330.017us 10 10 100.00
watermark 20 20 100.00
uart_tx_rx 181.000s 113819.909us 10 10 100.00
uart_intr 774.000s 573530.426us 10 10 100.00
fifo_full 10 10 100.00
uart_fifo_full 154.000s 191610.282us 10 10 100.00
fifo_overflow 10 10 100.00
uart_fifo_overflow 96.000s 114931.007us 10 10 100.00
fifo_reset 200 200 100.00
uart_fifo_reset 370.000s 179186.161us 200 200 100.00
rx_frame_err 10 10 100.00
uart_intr 774.000s 573530.426us 10 10 100.00
rx_break_err 10 10 100.00
uart_intr 774.000s 573530.426us 10 10 100.00
rx_timeout 10 10 100.00
uart_intr 774.000s 573530.426us 10 10 100.00
perf 10 10 100.00
uart_perf 553.000s 20733.960us 10 10 100.00
sys_loopback 10 10 100.00
uart_loopback 24.000s 13048.564us 10 10 100.00
line_loopback 10 10 100.00
uart_loopback 24.000s 13048.564us 10 10 100.00
rx_noise_filter 2 10 20.00
uart_noise_filter 43.000s 135441.527us 2 10 20.00
rx_start_bit_filter 10 10 100.00
uart_rx_start_bit_filter 38.000s 30563.992us 10 10 100.00
tx_overide 10 10 100.00
uart_tx_ovrd 39.000s 12144.249us 10 10 100.00
rx_oversample 10 10 100.00
uart_rx_oversample 24.000s 4702.881us 10 10 100.00
long_b2b_transfer 10 10 100.00
uart_long_xfer_wo_dly 997.000s 138189.553us 10 10 100.00
stress_all 7 10 70.00
uart_stress_all 1146.000s 393446.045us 7 10 70.00
alert_test 10 10 100.00
uart_alert_test 2.000s 70.700us 10 10 100.00
intr_test 10 10 100.00
uart_intr_test 2.000s 13.646us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
uart_tl_errors 3.000s 243.063us 25 25 100.00
tl_d_illegal_access 25 25 100.00
uart_tl_errors 3.000s 243.063us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
uart_csr_hw_reset 2.000s 93.795us 1 1 100.00
uart_csr_rw 2.000s 12.470us 5 5 100.00
uart_csr_aliasing 2.000s 87.814us 1 1 100.00
uart_same_csr_outstanding 2.000s 107.115us 5 5 100.00
tl_d_partial_access 12 12 100.00
uart_csr_hw_reset 2.000s 93.795us 1 1 100.00
uart_csr_rw 2.000s 12.470us 5 5 100.00
uart_csr_aliasing 2.000s 87.814us 1 1 100.00
uart_same_csr_outstanding 2.000s 107.115us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
uart_sec_cm 2.000s 511.103us 5 5 100.00
uart_tl_intg_err 3.000s 343.182us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
uart_tl_intg_err 3.000s 343.182us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
uart_stress_all_with_rand_reset 70.000s 9297.763us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 8 test runs
uart_noise_filter 5101172536272880232191396558796414483777922438704374857418037802010005104568 87
UVM_ERROR @ 17649602165 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 17649642165 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (129 [0x81] vs 249 [0xf9]) reg name: uart_reg_block.rdata
UVM_ERROR @ 17649722165 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 17649842165 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (129 [0x81] vs 191 [0xbf]) reg name: uart_reg_block.rdata
uart_noise_filter 5159399629930427942764095736755747775418330770420846787239251726881401938157 84
UVM_ERROR @ 777211199 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 777221300 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (135 [0x87] vs 191 [0xbf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 777241502 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 777251603 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (135 [0x87] vs 255 [0xff]) reg name: uart_reg_block.rdata
uart_noise_filter 96679745041497539435189307197235211345657487756766689347963706496691038296967 91
UVM_ERROR @ 59035846764 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 59412286764 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 59412286764 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 59412286764 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
uart_stress_all 101324946249107811204641642126762300572787301991740977783308932779975210239989 102
UVM_ERROR @ 125876390774 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 125876618049 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata
UVM_ERROR @ 125876708959 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 125876936234 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 124 [0x7c]) reg name: uart_reg_block.rdata
uart_noise_filter 109859876927269227455092620824961662967815689177036454558075945052316955382989 83
UVM_ERROR @ 137463973 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 137474282 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 239 [0xef]) reg name: uart_reg_block.rdata
UVM_ERROR @ 229492416 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 229492416 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all 52028306454120996712409833215590831552888559505530352690521967981907550851802 104
UVM_ERROR @ 393109259044 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 393109279877 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 393109321543 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 393109342376 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata
uart_stress_all 34958399675288345516237423040689440300575799529621231985330670054334797658176 85
UVM_ERROR @ 5614938425 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 5615020057 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (201 [0xc9] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 5615060873 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 5615244545 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (201 [0xc9] vs 63 [0x3f]) reg name: uart_reg_block.rdata
uart_noise_filter 114459386759267420489222546697172408354380071132223256532765154065189072229384 87
UVM_ERROR @ 10904346455 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 10904361380 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (161 [0xa1] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 10927689155 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 10927719005 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 4 test runs
uart_noise_filter 27415209383656525972629146328132142409582099324041146103526511636217001088708 83
UVM_ERROR @ 8719892 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 103538100 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 5, clk_pulses: 0
UVM_ERROR @ 103653886 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 103685464 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata
uart_noise_filter 60560590581608275046016282504971137080989345667052287343264746302671005739640 90
UVM_ERROR @ 24381589426 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 24381589426 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 24389444722 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 24389444722 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 43117195963187054574351751424808882466980554435834974452213398155672214240227 83
UVM_ERROR @ 15056872 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 15698958 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 16214732 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 16719980 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all_with_rand_reset 24894326618925994105576849071952174402406866445771525193166424695322551240180 97
UVM_ERROR @ 657440796 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 657956570 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 658251298 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 663230096 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:446) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr 1 test run
uart_stress_all_with_rand_reset 72465567174010604919298261904981710962327268042521193546445647120410852949382 186
UVM_INFO @ 5758079867 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 7/10
UVM_INFO @ 5758207529 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Stress w/ reset is done for run 7/10