| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| unmapped |
|
93.55% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_memory_smoke | 25 | 25 | 100.00 | |||
| dma_memory_smoke | 9.000s | 3378.521us | 25 | 25 | 100.00 | |
| dma_handshake_smoke | 25 | 25 | 100.00 | |||
| dma_handshake_smoke | 9.000s | 2162.942us | 25 | 25 | 100.00 | |
| dma_generic_smoke | 50 | 50 | 100.00 | |||
| dma_generic_smoke | 8.000s | 2055.872us | 50 | 50 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 20.917us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| dma_csr_rw | 2.000s | 106.364us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| dma_csr_bit_bash | 11.000s | 3224.400us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| dma_csr_aliasing | 9.000s | 497.859us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| dma_csr_mem_rw_with_rand_reset | 2.000s | 79.185us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| dma_csr_rw | 2.000s | 106.364us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 9.000s | 497.859us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_memory_region_lock | 5 | 5 | 100.00 | |||
| dma_memory_region_lock | 138.000s | 5414.679us | 5 | 5 | 100.00 | |
| dma_memory_tl_error | 3 | 3 | 100.00 | |||
| dma_memory_stress | 1139.000s | 160915.351us | 3 | 3 | 100.00 | |
| dma_handshake_tl_error | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 882.000s | 69764.685us | 3 | 3 | 100.00 | |
| dma_handshake_stress | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 882.000s | 69764.685us | 3 | 3 | 100.00 | |
| dma_memory_stress | 3 | 3 | 100.00 | |||
| dma_memory_stress | 1139.000s | 160915.351us | 3 | 3 | 100.00 | |
| dma_generic_stress | 5 | 5 | 100.00 | |||
| dma_generic_stress | 815.000s | 55745.231us | 5 | 5 | 100.00 | |
| dma_handshake_mem_buffer_overflow | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 882.000s | 69764.685us | 3 | 3 | 100.00 | |
| dma_abort | 5 | 5 | 100.00 | |||
| dma_abort | 19.000s | 1205.497us | 5 | 5 | 100.00 | |
| dma_stress_all | 3 | 3 | 100.00 | |||
| dma_stress_all | 275.000s | 15519.728us | 3 | 3 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| dma_alert_test | 2.000s | 29.571us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| dma_intr_test | 2.000s | 29.039us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| dma_tl_errors | 4.000s | 161.445us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| dma_tl_errors | 4.000s | 161.445us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 20.917us | 1 | 1 | 100.00 | |
| dma_csr_rw | 2.000s | 106.364us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 9.000s | 497.859us | 1 | 1 | 100.00 | |
| dma_same_csr_outstanding | 3.000s | 113.380us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 20.917us | 1 | 1 | 100.00 | |
| dma_csr_rw | 2.000s | 106.364us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 9.000s | 497.859us | 1 | 1 | 100.00 | |
| dma_same_csr_outstanding | 3.000s | 113.380us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_illegal_addr_range | 13 | 13 | 100.00 | |||
| dma_mem_enabled | 28.000s | 4817.744us | 5 | 5 | 100.00 | |
| dma_generic_stress | 815.000s | 55745.231us | 5 | 5 | 100.00 | |
| dma_handshake_stress | 882.000s | 69764.685us | 3 | 3 | 100.00 | |
| dma_config_lock | 15 | 15 | 100.00 | |||
| dma_config_lock | 12.000s | 2038.603us | 15 | 15 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| dma_tl_intg_err | 5.000s | 731.592us | 25 | 25 | 100.00 | |
| dma_sec_cm | 2.000s | 29.461us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 29 | 31 | 93.55 | |||
| dma_short_transfer | 220.000s | 61547.330us | 24 | 25 | 96.00 | |
| dma_longer_transfer | 215.000s | 10331.246us | 5 | 5 | 100.00 | |
| dma_stress_all_with_rand_reset | 13.000s | 2117.090us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| dma_stress_all_with_rand_reset | 52415716657381618123372836862491067343323491627299126875743678441524761339915 | 106 |
UVM_INFO @ 2117089791ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ *ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of *ps hit, indicating a probable testbench issue | 1 test run | |||
| dma_short_transfer | 19633967044469497682876528798306182511517474738184993400882739239614327126316 | 1587 |
UVM_INFO @ 200000000000ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|