Simulation Results

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke	0	5	0.00
	aon_timer_smoke	0.856s	0.000us	0	5	0.00
csr_hw_reset	0	1	0.00
	aon_timer_csr_hw_reset	0.853s	0.000us	0	1	0.00
csr_rw	0	5	0.00
	aon_timer_csr_rw	0.872s	0.000us	0	5	0.00
csr_bit_bash	0	1	0.00
	aon_timer_csr_bit_bash	0.844s	0.000us	0	1	0.00
csr_aliasing	0	1	0.00
	aon_timer_csr_aliasing	0.860s	0.000us	0	1	0.00
csr_mem_rw_with_rand_reset	0	5	0.00
	aon_timer_csr_mem_rw_with_rand_reset	0.861s	0.000us	0	5	0.00
regwen_csr_and_corresponding_lockable_csr	0	6	0.00
	aon_timer_csr_rw	0.872s	0.000us	0	5	0.00
	aon_timer_csr_aliasing	0.860s	0.000us	0	1	0.00
mem_walk	0	1	0.00
	aon_timer_mem_walk	0.865s	0.000us	0	1	0.00
mem_partial_access	0	1	0.00
	aon_timer_mem_partial_access	0.888s	0.000us	0	1	0.00

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
prescaler	0	15	0.00
	aon_timer_prescaler	0.917s	0.000us	0	15	0.00
jump	0	5	0.00
	aon_timer_jump	0.882s	0.000us	0	5	0.00
stress_all	15	15	100.00
	aon_timer_stress_all	104.000s	160067.087us	15	15	100.00
alert_test	0	10	0.00
	aon_timer_alert_test	1.312s	0.000us	0	10	0.00
intr_test	0	10	0.00
	aon_timer_intr_test	1.383s	0.000us	0	10	0.00
tl_d_oob_addr_access	0	25	0.00
	aon_timer_tl_errors	1.333s	0.000us	0	25	0.00
tl_d_illegal_access	0	25	0.00
	aon_timer_tl_errors	1.333s	0.000us	0	25	0.00
tl_d_outstanding_access	0	12	0.00
	aon_timer_csr_hw_reset	0.853s	0.000us	0	1	0.00
	aon_timer_csr_rw	0.872s	0.000us	0	5	0.00
	aon_timer_csr_aliasing	0.860s	0.000us	0	1	0.00
	aon_timer_same_csr_outstanding	0.876s	0.000us	0	5	0.00
tl_d_partial_access	0	12	0.00
	aon_timer_csr_hw_reset	0.853s	0.000us	0	1	0.00
	aon_timer_csr_rw	0.872s	0.000us	0	5	0.00
	aon_timer_csr_aliasing	0.860s	0.000us	0	1	0.00
	aon_timer_same_csr_outstanding	0.876s	0.000us	0	5	0.00

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err	0	30	0.00
	aon_timer_sec_cm	1.322s	0.000us	0	5	0.00
	aon_timer_tl_intg_err	1.893s	0.000us	0	25	0.00
sec_cm_bus_integrity	0	25	0.00
	aon_timer_tl_intg_err	1.893s	0.000us	0	25	0.00

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_threshold	0	5	0.00
	aon_timer_smoke_max_thold	0.854s	0.000us	0	5	0.00
min_threshold	0	5	0.00
	aon_timer_smoke_min_thold	0.865s	0.000us	0	5	0.00
wkup_count_hi_cdc	0	5	0.00
	aon_timer_wkup_count_cdc_hi	0.879s	0.000us	0	5	0.00
custom_intr	0	10	0.00
	aon_timer_custom_intr	1.389s	0.000us	0	10	0.00
alternating_on_off	0	5	0.00
	aon_timer_alternating_enable_on_off	0.892s	0.000us	0	5	0.00
stress_all_with_rand_reset	0	15	0.00
	aon_timer_stress_all_with_rand_reset	1.392s	0.000us	0	15	0.00

Error Messages

V1		0.00%
V2		16.30%
V2S		0.00%
V3		0.00%

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				165 test runs
	aon_timer_smoke	72241613363164772076374237310755515865016520998307752526648796592491408592198	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1258753350 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/0.aon_timer_smoke.1258753350 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 0.aon_timer_smoke.1258753350 -covoverwrite' seed=72241613363164772076374237310755515865016520998307752526648796592491408592198 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72241613363164772076374237310755515865016520998307752526648796592491408592198 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_prescaler	1198389946270436590121430560076924509694356574352176708353395276781076458317	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_prescaler/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=258583373 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/0.aon_timer_prescaler.258583373 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 0.aon_timer_prescaler.258583373 -covoverwrite' seed=1198389946270436590121430560076924509694356574352176708353395276781076458317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1198389946270436590121430560076924509694356574352176708353395276781076458317 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_prescaler/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_prescaler_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_jump	113065239615124274291669215106373568953647519697471125752027058317937594089723	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_jump/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1155547387 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/0.aon_timer_jump.1155547387 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 0.aon_timer_jump.1155547387 -covoverwrite' seed=113065239615124274291669215106373568953647519697471125752027058317937594089723 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113065239615124274291669215106373568953647519697471125752027058317937594089723 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_jump/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_jump_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_custom_intr	46180092838659354686460688210274006390942980227624594230548393479413082635063	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_custom_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=721959735 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_custom_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/0.aon_timer_custom_intr.721959735 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 0.aon_timer_custom_intr.721959735 -covoverwrite' seed=46180092838659354686460688210274006390942980227624594230548393479413082635063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46180092838659354686460688210274006390942980227624594230548393479413082635063 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_custom_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_custom_intr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_smoke_max_thold	28631851387763767895827519144704183954200297277987086274787532082015488894213	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_smoke_max_thold/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3527599365 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_max_thold_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/0.aon_timer_smoke_max_thold.3527599365 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 0.aon_timer_smoke_max_thold.3527599365 -covoverwrite' seed=28631851387763767895827519144704183954200297277987086274787532082015488894213 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28631851387763767895827519144704183954200297277987086274787532082015488894213 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_smoke_max_thold/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_smoke_max_thold_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_smoke_min_thold	99418809679363151112318242703806950999849618452769340484061656621789605726721	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_smoke_min_thold/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1854867969 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_min_thold_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/0.aon_timer_smoke_min_thold.1854867969 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 0.aon_timer_smoke_min_thold.1854867969 -covoverwrite' seed=99418809679363151112318242703806950999849618452769340484061656621789605726721 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99418809679363151112318242703806950999849618452769340484061656621789605726721 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_smoke_min_thold/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_smoke_min_thold_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_wkup_count_cdc_hi	8434439530501769394037631041695483269536150026741939219074435608735167647389	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_wkup_count_cdc_hi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2575404701 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_wkup_count_cdc_hi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/0.aon_timer_wkup_count_cdc_hi.2575404701 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 0.aon_timer_wkup_count_cdc_hi.2575404701 -covoverwrite' seed=8434439530501769394037631041695483269536150026741939219074435608735167647389 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8434439530501769394037631041695483269536150026741939219074435608735167647389 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_wkup_count_cdc_hi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_wkup_count_cdc_hi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_alternating_enable_on_off	73898464504379908444006701280856610099425719557523307764145093438796796367190	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_alternating_enable_on_off/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3010302294 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_alternating_enable_on_off_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/0.aon_timer_alternating_enable_on_off.3010302294 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 0.aon_timer_alternating_enable_on_off.3010302294 -covoverwrite' seed=73898464504379908444006701280856610099425719557523307764145093438796796367190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73898464504379908444006701280856610099425719557523307764145093438796796367190 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_alternating_enable_on_off/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_alternating_enable_on_off_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_stress_all_with_rand_reset	77038293359901420666387842434253235046985917255054957227583484277364436450200	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2711305112 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/0.aon_timer_stress_all_with_rand_reset.2711305112 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 0.aon_timer_stress_all_with_rand_reset.2711305112 -covoverwrite' seed=77038293359901420666387842434253235046985917255054957227583484277364436450200 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77038293359901420666387842434253235046985917255054957227583484277364436450200 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_sec_cm	36347139974820053010203632420305451390150966783383115012674297529234409771745	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1997656801 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/0.aon_timer_sec_cm.1997656801 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 0.aon_timer_sec_cm.1997656801 -covoverwrite' seed=36347139974820053010203632420305451390150966783383115012674297529234409771745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36347139974820053010203632420305451390150966783383115012674297529234409771745 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_tl_errors	91469170033149915010101436181251129408135228791999711861662970329811082606012	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1413805500 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/0.aon_timer_tl_errors.1413805500 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aon_timer_tl_errors.1413805500 -covoverwrite' seed=91469170033149915010101436181251129408135228791999711861662970329811082606012 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91469170033149915010101436181251129408135228791999711861662970329811082606012 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_tl_intg_err	1799361671704897831767520350833612372979882298595737435564325271021015407006	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2055870878 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2055870878 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aon_timer_tl_intg_err.2055870878 -covoverwrite' seed=1799361671704897831767520350833612372979882298595737435564325271021015407006 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1799361671704897831767520350833612372979882298595737435564325271021015407006 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_intr_test	101738555621182627541267218597009441947644167205329591155802980446498369970526	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2445680990 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/0.aon_timer_intr_test.2445680990 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aon_timer_intr_test.2445680990 -covoverwrite' seed=101738555621182627541267218597009441947644167205329591155802980446498369970526 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101738555621182627541267218597009441947644167205329591155802980446498369970526 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_alert_test	7108932842357662939333113353543437634486773494932115215694408579069483708796	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=4021580156 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/0.aon_timer_alert_test.4021580156 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 0.aon_timer_alert_test.4021580156 -covoverwrite' seed=7108932842357662939333113353543437634486773494932115215694408579069483708796 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7108932842357662939333113353543437634486773494932115215694408579069483708796 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_mem_walk	69548890720498990531861894467118000307943893826767925607275201419638648849048	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_mem_walk/latest run_opts='+csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=524272280 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/0.aon_timer_mem_walk.524272280 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aon_timer_mem_walk.524272280 -covoverwrite' seed=69548890720498990531861894467118000307943893826767925607275201419638648849048 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69548890720498990531861894467118000307943893826767925607275201419638648849048 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_mem_partial_access	45569086779140580840898117477355496178479099470620446642147358287828005169623	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_mem_partial_access/latest run_opts='+run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3846449623 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3846449623 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aon_timer_mem_partial_access.3846449623 -covoverwrite' seed=45569086779140580840898117477355496178479099470620446642147358287828005169623 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45569086779140580840898117477355496178479099470620446642147358287828005169623 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_csr_hw_reset	33248606507106402011112579487240673188144331046347386334243178008398447946586	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=254978906 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.254978906 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aon_timer_csr_hw_reset.254978906 -covoverwrite' seed=33248606507106402011112579487240673188144331046347386334243178008398447946586 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33248606507106402011112579487240673188144331046347386334243178008398447946586 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_csr_rw	95702961312515688141795443996781814983097574449059846316900478638794081654928	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2416269456 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/0.aon_timer_csr_rw.2416269456 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aon_timer_csr_rw.2416269456 -covoverwrite' seed=95702961312515688141795443996781814983097574449059846316900478638794081654928 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95702961312515688141795443996781814983097574449059846316900478638794081654928 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_csr_bit_bash	37382239690495910810046653260707897393624786521829089834377761196678425963289	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3729615641 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3729615641 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aon_timer_csr_bit_bash.3729615641 -covoverwrite' seed=37382239690495910810046653260707897393624786521829089834377761196678425963289 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37382239690495910810046653260707897393624786521829089834377761196678425963289 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_csr_aliasing	72436735275996075491426984927386515050393989607774997327844556499223645179054	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3761687726 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3761687726 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aon_timer_csr_aliasing.3761687726 -covoverwrite' seed=72436735275996075491426984927386515050393989607774997327844556499223645179054 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72436735275996075491426984927386515050393989607774997327844556499223645179054 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_same_csr_outstanding	85089406330631748548018625289897233444078439210676894976442329225967506832573	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=247217341 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.247217341 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aon_timer_same_csr_outstanding.247217341 -covoverwrite' seed=85089406330631748548018625289897233444078439210676894976442329225967506832573 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85089406330631748548018625289897233444078439210676894976442329225967506832573 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_csr_mem_rw_with_rand_reset	74055056819640853437876409310552286350143123856488306106032778853589890480947	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1916123955 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1916123955 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aon_timer_csr_mem_rw_with_rand_reset.1916123955 -covoverwrite' seed=74055056819640853437876409310552286350143123856488306106032778853589890480947 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74055056819640853437876409310552286350143123856488306106032778853589890480947 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/0.aon_timer_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_smoke	36791127398953595782968408240613423378743587671285495329740461266174877365632	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3022517632 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/1.aon_timer_smoke.3022517632 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 1.aon_timer_smoke.3022517632 -covoverwrite' seed=36791127398953595782968408240613423378743587671285495329740461266174877365632 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36791127398953595782968408240613423378743587671285495329740461266174877365632 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_prescaler	50718146831808286608573338407992762346900228243887954090674155195628783691043	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_prescaler/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2950718755 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/1.aon_timer_prescaler.2950718755 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 1.aon_timer_prescaler.2950718755 -covoverwrite' seed=50718146831808286608573338407992762346900228243887954090674155195628783691043 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50718146831808286608573338407992762346900228243887954090674155195628783691043 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_prescaler/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_prescaler_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_jump	88897986214033703089031359905831054631767854710047692168588899656050897060516	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_jump/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1148191396 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/1.aon_timer_jump.1148191396 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 1.aon_timer_jump.1148191396 -covoverwrite' seed=88897986214033703089031359905831054631767854710047692168588899656050897060516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88897986214033703089031359905831054631767854710047692168588899656050897060516 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_jump/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_jump_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_custom_intr	42607373139442066546752204292006251063741456751024083833771607131352318512646	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_custom_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3334376966 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_custom_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/1.aon_timer_custom_intr.3334376966 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 1.aon_timer_custom_intr.3334376966 -covoverwrite' seed=42607373139442066546752204292006251063741456751024083833771607131352318512646 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42607373139442066546752204292006251063741456751024083833771607131352318512646 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_custom_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_custom_intr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_smoke_max_thold	73327591353642289160219052682223754044152414046669403642069734121889429198299	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_smoke_max_thold/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2943882715 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_max_thold_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/1.aon_timer_smoke_max_thold.2943882715 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 1.aon_timer_smoke_max_thold.2943882715 -covoverwrite' seed=73327591353642289160219052682223754044152414046669403642069734121889429198299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73327591353642289160219052682223754044152414046669403642069734121889429198299 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_smoke_max_thold/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_smoke_max_thold_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_smoke_min_thold	63905703909196790045843975265526047019675034654158468901421068213897547438612	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_smoke_min_thold/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2158189076 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_min_thold_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/1.aon_timer_smoke_min_thold.2158189076 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 1.aon_timer_smoke_min_thold.2158189076 -covoverwrite' seed=63905703909196790045843975265526047019675034654158468901421068213897547438612 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63905703909196790045843975265526047019675034654158468901421068213897547438612 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_smoke_min_thold/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_smoke_min_thold_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_wkup_count_cdc_hi	78466418522468264935131172093380148985968840550129040985627938996082973703715	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_wkup_count_cdc_hi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2192408099 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_wkup_count_cdc_hi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/1.aon_timer_wkup_count_cdc_hi.2192408099 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 1.aon_timer_wkup_count_cdc_hi.2192408099 -covoverwrite' seed=78466418522468264935131172093380148985968840550129040985627938996082973703715 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78466418522468264935131172093380148985968840550129040985627938996082973703715 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_wkup_count_cdc_hi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_wkup_count_cdc_hi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_alternating_enable_on_off	51665934119477268295865168214438711925404545413642900473183727377866174513730	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_alternating_enable_on_off/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3572253250 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_alternating_enable_on_off_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/1.aon_timer_alternating_enable_on_off.3572253250 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 1.aon_timer_alternating_enable_on_off.3572253250 -covoverwrite' seed=51665934119477268295865168214438711925404545413642900473183727377866174513730 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51665934119477268295865168214438711925404545413642900473183727377866174513730 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_alternating_enable_on_off/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_alternating_enable_on_off_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_stress_all_with_rand_reset	45856426138104014432217696892336955763398667848812232663004478599215201380415	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1238100031 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/1.aon_timer_stress_all_with_rand_reset.1238100031 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 1.aon_timer_stress_all_with_rand_reset.1238100031 -covoverwrite' seed=45856426138104014432217696892336955763398667848812232663004478599215201380415 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45856426138104014432217696892336955763398667848812232663004478599215201380415 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_sec_cm	86308046232093317179622686815961576472649054428858822578501369077295374711516	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=4285315804 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/1.aon_timer_sec_cm.4285315804 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 1.aon_timer_sec_cm.4285315804 -covoverwrite' seed=86308046232093317179622686815961576472649054428858822578501369077295374711516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86308046232093317179622686815961576472649054428858822578501369077295374711516 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_tl_errors	40320441764718218807222519713528681745504492182175545669405930114062778590641	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1524065713 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/1.aon_timer_tl_errors.1524065713 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.aon_timer_tl_errors.1524065713 -covoverwrite' seed=40320441764718218807222519713528681745504492182175545669405930114062778590641 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40320441764718218807222519713528681745504492182175545669405930114062778590641 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_tl_intg_err	22776147353366249959779626138393904402632878133263975131451846274747924252188	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3698624028 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3698624028 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.aon_timer_tl_intg_err.3698624028 -covoverwrite' seed=22776147353366249959779626138393904402632878133263975131451846274747924252188 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22776147353366249959779626138393904402632878133263975131451846274747924252188 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_intr_test	7984152699281633463625247672177127375075131860323581283404922068752264666737	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1994989169 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/1.aon_timer_intr_test.1994989169 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.aon_timer_intr_test.1994989169 -covoverwrite' seed=7984152699281633463625247672177127375075131860323581283404922068752264666737 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7984152699281633463625247672177127375075131860323581283404922068752264666737 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_alert_test	28973179572545644544482303187634052303406990748668325405200754601635242909973	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=768942357 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/default/1.aon_timer_alert_test.768942357 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope default -covtest 1.aon_timer_alert_test.768942357 -covoverwrite' seed=28973179572545644544482303187634052303406990748668325405200754601635242909973 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28973179572545644544482303187634052303406990748668325405200754601635242909973 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_csr_rw	84427695852028361570839503459749343720963996301824107738895763656015365153014	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3779731702 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/1.aon_timer_csr_rw.3779731702 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.aon_timer_csr_rw.3779731702 -covoverwrite' seed=84427695852028361570839503459749343720963996301824107738895763656015365153014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84427695852028361570839503459749343720963996301824107738895763656015365153014 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_same_csr_outstanding	1373481603109149211090152648865338131021283843401042663767262867557179721303	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=799540823 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.799540823 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.aon_timer_same_csr_outstanding.799540823 -covoverwrite' seed=1373481603109149211090152648865338131021283843401042663767262867557179721303 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1373481603109149211090152648865338131021283843401042663767262867557179721303 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aon_timer_csr_mem_rw_with_rand_reset	30234358893676833617094956719537648426555382521101952554978549977656954063994	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aon_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2674789498 +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2674789498 -covworkdir /nightly/current_run/scratch/master/aon_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.aon_timer_csr_mem_rw_with_rand_reset.2674789498 -covoverwrite' seed=30234358893676833617094956719537648426555382521101952554978549977656954063994 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30234358893676833617094956719537648426555382521101952554978549977656954063994 --run-dir=/nightly/current_run/scratch/master/aon_timer-sim-xcelium/1.aon_timer_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aon_timer_base_test uvm_test_seq=aon_timer_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126

Simulation Results: aon_timer

Error Messages