Simulation Results

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke	0	10	0.00
	edn_smoke	1.932s	0.000us	0	10	0.00
csr_hw_reset	0	1	0.00
	edn_csr_hw_reset	0.841s	0.000us	0	1	0.00
csr_rw	0	5	0.00
	edn_csr_rw	1.320s	0.000us	0	5	0.00
csr_bit_bash	0	1	0.00
	edn_csr_bit_bash	0.836s	0.000us	0	1	0.00
csr_aliasing	0	1	0.00
	edn_csr_aliasing	0.841s	0.000us	0	1	0.00
csr_mem_rw_with_rand_reset	0	5	0.00
	edn_csr_mem_rw_with_rand_reset	0.867s	0.000us	0	5	0.00
regwen_csr_and_corresponding_lockable_csr	0	6	0.00
	edn_csr_rw	1.320s	0.000us	0	5	0.00
	edn_csr_aliasing	0.841s	0.000us	0	1	0.00

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
firmware	0	100	0.00
	edn_genbits	1.431s	0.000us	0	100	0.00
csrng_commands	0	100	0.00
	edn_genbits	1.431s	0.000us	0	100	0.00
genbits	0	100	0.00
	edn_genbits	1.431s	0.000us	0	100	0.00
interrupts	0	20	0.00
	edn_intr	1.411s	0.000us	0	20	0.00
alerts	0	200	0.00
	edn_alert	1.420s	0.000us	0	200	0.00
errs	0	100	0.00
	edn_err	1.419s	0.000us	0	100	0.00
disable	0	100	0.00
	edn_disable	0.895s	0.000us	0	50	0.00
	edn_disable_auto_req_mode	1.417s	0.000us	0	50	0.00
stress_all	30	30	100.00
	edn_stress_all	6.460s	342.348us	30	30	100.00
intr_test	0	10	0.00
	edn_intr_test	0.854s	0.000us	0	10	0.00
alert_test	0	10	0.00
	edn_alert_test	1.365s	0.000us	0	10	0.00
tl_d_oob_addr_access	0	25	0.00
	edn_tl_errors	1.372s	0.000us	0	25	0.00
tl_d_illegal_access	0	25	0.00
	edn_tl_errors	1.372s	0.000us	0	25	0.00
tl_d_outstanding_access	0	12	0.00
	edn_csr_hw_reset	0.841s	0.000us	0	1	0.00
	edn_csr_rw	1.320s	0.000us	0	5	0.00
	edn_csr_aliasing	0.841s	0.000us	0	1	0.00
	edn_same_csr_outstanding	1.362s	0.000us	0	5	0.00
tl_d_partial_access	0	12	0.00
	edn_csr_hw_reset	0.841s	0.000us	0	1	0.00
	edn_csr_rw	1.320s	0.000us	0	5	0.00
	edn_csr_aliasing	0.841s	0.000us	0	1	0.00
	edn_same_csr_outstanding	1.362s	0.000us	0	5	0.00

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err	0	30	0.00
	edn_sec_cm	1.434s	0.000us	0	5	0.00
	edn_tl_intg_err	1.410s	0.000us	0	25	0.00
sec_cm_config_regwen	0	5	0.00
	edn_regwen	1.429s	0.000us	0	5	0.00
sec_cm_config_mubi	0	200	0.00
	edn_alert	1.420s	0.000us	0	200	0.00
sec_cm_main_sm_fsm_sparse	0	5	0.00
	edn_sec_cm	1.434s	0.000us	0	5	0.00
sec_cm_ack_sm_fsm_sparse	0	5	0.00
	edn_sec_cm	1.434s	0.000us	0	5	0.00
sec_cm_fifo_ctr_redun	0	5	0.00
	edn_sec_cm	1.434s	0.000us	0	5	0.00
sec_cm_ctr_redun	0	5	0.00
	edn_sec_cm	1.434s	0.000us	0	5	0.00
sec_cm_main_sm_ctr_local_esc	0	205	0.00
	edn_alert	1.420s	0.000us	0	200	0.00
	edn_sec_cm	1.434s	0.000us	0	5	0.00
sec_cm_cs_rdata_bus_consistency	0	200	0.00
	edn_alert	1.420s	0.000us	0	200	0.00
sec_cm_tile_link_bus_integrity	0	25	0.00
	edn_tl_intg_err	1.410s	0.000us	0	25	0.00

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset	0	30	0.00
	edn_stress_all_with_rand_reset	1.376s	0.000us	0	30	0.00

Error Messages

V1		0.00%
V2		4.94%
V2S		0.00%
V3		0.00%

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				658 test runs
	edn_smoke	59331919253176382546560035316302780343220940339369538291716657332315782226013	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3945111645 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3945111645' seed=59331919253176382546560035316302780343220940339369538291716657332315782226013 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59331919253176382546560035316302780343220940339369538291716657332315782226013 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_smoke_test uvm_test_seq=edn_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_regwen	91511083159584431267150362807420273309730779326851980224877446640468598477052	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_regwen/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=313807100 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.313807100' seed=91511083159584431267150362807420273309730779326851980224877446640468598477052 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91511083159584431267150362807420273309730779326851980224877446640468598477052 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_regwen_test uvm_test_seq=edn_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_genbits	87807514526537247015235496166429399835338138992298078514525317219842481601551	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2116434959 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2116434959' seed=87807514526537247015235496166429399835338138992298078514525317219842481601551 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87807514526537247015235496166429399835338138992298078514525317219842481601551 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_stress_all_with_rand_reset	49276371857325515962102951297935041615155314996146646389747948286083125488032	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1779444128 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.1779444128' seed=49276371857325515962102951297935041615155314996146646389747948286083125488032 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49276371857325515962102951297935041615155314996146646389747948286083125488032 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_intr	56345970825130094810676681760820467948020229850192727394581832516636850390514	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2823161330 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2823161330' seed=56345970825130094810676681760820467948020229850192727394581832516636850390514 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56345970825130094810676681760820467948020229850192727394581832516636850390514 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_alert	8711669250725567647129261620365278589881825983404747314357577064005738151600	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=207863472 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.207863472' seed=8711669250725567647129261620365278589881825983404747314357577064005738151600 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8711669250725567647129261620365278589881825983404747314357577064005738151600 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_err	30429838994325850987733406165548376282471478553041751895599065947976680295253	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2399882069 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2399882069' seed=30429838994325850987733406165548376282471478553041751895599065947976680295253 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30429838994325850987733406165548376282471478553041751895599065947976680295253 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_disable	9816617489343174984377847484815347827696868119905015967780593041653416479188	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=720783828 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.720783828' seed=9816617489343174984377847484815347827696868119905015967780593041653416479188 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9816617489343174984377847484815347827696868119905015967780593041653416479188 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_disable_auto_req_mode	27264636889245951729000802053873046957361173342045671826052678797314092286482	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=612745746 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable_auto_req_mode.612745746' seed=27264636889245951729000802053873046957361173342045671826052678797314092286482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27264636889245951729000802053873046957361173342045671826052678797314092286482 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_sec_cm	42231375536550358827081429310665375347420371771154893706060635034184863371975	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=515035847 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.515035847' seed=42231375536550358827081429310665375347420371771154893706060635034184863371975 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42231375536550358827081429310665375347420371771154893706060635034184863371975 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_tl_errors	68764572567177535081316980698875848745866255154464775482445326515937661473678	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1994707854 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1994707854' seed=68764572567177535081316980698875848745866255154464775482445326515937661473678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68764572567177535081316980698875848745866255154464775482445326515937661473678 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_tl_intg_err	19469175989505456992183545824954967118437523248744638188890397922156507999596	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3222449516 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3222449516' seed=19469175989505456992183545824954967118437523248744638188890397922156507999596 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19469175989505456992183545824954967118437523248744638188890397922156507999596 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_alert_test	88547809530377688646501904148087603247997969843545412280871452196666258962270	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2771859294 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2771859294' seed=88547809530377688646501904148087603247997969843545412280871452196666258962270 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88547809530377688646501904148087603247997969843545412280871452196666258962270 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_intr_test	58218270608658796100246152254320228858550941992114524644671789463111903943275	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=569055851 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.569055851' seed=58218270608658796100246152254320228858550941992114524644671789463111903943275 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58218270608658796100246152254320228858550941992114524644671789463111903943275 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_csr_hw_reset	62744092220014976483955977994170761570709988402291957247498349054275729439555	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=840383299 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.840383299' seed=62744092220014976483955977994170761570709988402291957247498349054275729439555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62744092220014976483955977994170761570709988402291957247498349054275729439555 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_csr_rw	40426394131178692504473949968227379086745246585293429314665844897872929670056	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=192463784 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.192463784' seed=40426394131178692504473949968227379086745246585293429314665844897872929670056 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40426394131178692504473949968227379086745246585293429314665844897872929670056 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_csr_bit_bash	68684337516038133824668560950285756696138861838528302136320637346554271583504	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3861728528 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3861728528' seed=68684337516038133824668560950285756696138861838528302136320637346554271583504 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68684337516038133824668560950285756696138861838528302136320637346554271583504 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_csr_aliasing	80197617459461592443660551817020085135895518377614125903323276442654685918032	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4292735824 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.4292735824' seed=80197617459461592443660551817020085135895518377614125903323276442654685918032 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80197617459461592443660551817020085135895518377614125903323276442654685918032 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_same_csr_outstanding	4329569872885036818803564785554333784718387241193568700394588190362774563363	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2128898595 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.2128898595' seed=4329569872885036818803564785554333784718387241193568700394588190362774563363 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4329569872885036818803564785554333784718387241193568700394588190362774563363 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_csr_mem_rw_with_rand_reset	8919305171321473312541965467743748528470955017338985331894309801186557132118	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=483622230 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.483622230' seed=8919305171321473312541965467743748528470955017338985331894309801186557132118 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8919305171321473312541965467743748528470955017338985331894309801186557132118 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_smoke	19089237410110484663488138994354739090943397708595696966045135526198446624231	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1887407591 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1887407591' seed=19089237410110484663488138994354739090943397708595696966045135526198446624231 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19089237410110484663488138994354739090943397708595696966045135526198446624231 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_smoke_test uvm_test_seq=edn_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_regwen	94242191188549602895400002273554247366847691261836993744167079038096898980683	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_regwen/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2376006475 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2376006475' seed=94242191188549602895400002273554247366847691261836993744167079038096898980683 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94242191188549602895400002273554247366847691261836993744167079038096898980683 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_regwen_test uvm_test_seq=edn_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_genbits	51258728696412954083218650876269954393796005838267476230270358596982490136208	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_genbits/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2719088272 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2719088272' seed=51258728696412954083218650876269954393796005838267476230270358596982490136208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51258728696412954083218650876269954393796005838267476230270358596982490136208 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_genbits/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_genbits_test uvm_test_seq=edn_genbits_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_stress_all_with_rand_reset	70144568515343699434576780456582246166589812065964536745877237630858778036750	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=374786574 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.374786574' seed=70144568515343699434576780456582246166589812065964536745877237630858778036750 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70144568515343699434576780456582246166589812065964536745877237630858778036750 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_stress_all_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_intr	49915798030643336430745897184657937804726284774171730343539617561852670916069	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4046730725 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.4046730725' seed=49915798030643336430745897184657937804726284774171730343539617561852670916069 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49915798030643336430745897184657937804726284774171730343539617561852670916069 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_intr_test uvm_test_seq=edn_intr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_alert	74736327617691481274199537880124765336429831130578487905653997686206287471744	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=667313280 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.667313280' seed=74736327617691481274199537880124765336429831130578487905653997686206287471744 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74736327617691481274199537880124765336429831130578487905653997686206287471744 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_alert_test uvm_test_seq=edn_alert_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_err	15028084539500541041303790986524562837896525379688794213031896121461482569925	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3313615045 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3313615045' seed=15028084539500541041303790986524562837896525379688794213031896121461482569925 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15028084539500541041303790986524562837896525379688794213031896121461482569925 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_err_test uvm_test_seq=edn_err_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_disable	114332584983924388773008221090135968215002389608160501961513624448643383700295	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_disable/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3428854599 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3428854599' seed=114332584983924388773008221090135968215002389608160501961513624448643383700295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114332584983924388773008221090135968215002389608160501961513624448643383700295 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_disable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_test uvm_test_seq=edn_disable_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_disable_auto_req_mode	98096115952266951054630804517763389907152518250363946222145474415101794060551	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_disable_auto_req_mode/latest run_opts='+test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3404204295 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable_auto_req_mode.3404204295' seed=98096115952266951054630804517763389907152518250363946222145474415101794060551 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98096115952266951054630804517763389907152518250363946222145474415101794060551 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_disable_auto_req_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_disable_auto_req_mode_test uvm_test_seq=edn_disable_auto_req_mode_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_sec_cm	45024679628446223577582207144966396425880610532156408241573942067284427139149	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1782573133 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1782573133' seed=45024679628446223577582207144966396425880610532156408241573942067284427139149 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45024679628446223577582207144966396425880610532156408241573942067284427139149 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_tl_errors	30637352006842177058205142922878182838052580217702009384039190848277073411390	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3123756350 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3123756350' seed=30637352006842177058205142922878182838052580217702009384039190848277073411390 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30637352006842177058205142922878182838052580217702009384039190848277073411390 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_tl_intg_err	56496493930425748071680854110649030925587516036476876343146637562261156508205	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2916463149 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2916463149' seed=56496493930425748071680854110649030925587516036476876343146637562261156508205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56496493930425748071680854110649030925587516036476876343146637562261156508205 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_alert_test	43128905970470095061498909707671916848849211783733780969673693192466330206566	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1780138342 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1780138342' seed=43128905970470095061498909707671916848849211783733780969673693192466330206566 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43128905970470095061498909707671916848849211783733780969673693192466330206566 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_intr_test	72540246085776137316707980801892283618717036135639034714972621516643596931690	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3750138474 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3750138474' seed=72540246085776137316707980801892283618717036135639034714972621516643596931690 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72540246085776137316707980801892283618717036135639034714972621516643596931690 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_csr_rw	16328066449792573297857817363289610660801186376918087035527707092677281490607	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3663767215 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3663767215' seed=16328066449792573297857817363289610660801186376918087035527707092677281490607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16328066449792573297857817363289610660801186376918087035527707092677281490607 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_same_csr_outstanding	72524773579649998265660041697636233841426728253396537513449354592075075839957	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2702469077 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outstanding.2702469077' seed=72524773579649998265660041697636233841426728253396537513449354592075075839957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72524773579649998265660041697636233841426728253396537513449354592075075839957 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_csr_mem_rw_with_rand_reset	20609173648620910813378074148159842471768833191070878753321830615168048976217	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1268797785 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1268797785' seed=20609173648620910813378074148159842471768833191070878753321830615168048976217 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20609173648620910813378074148159842471768833191070878753321830615168048976217 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_base_test uvm_test_seq=edn_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_smoke	81172621278267072569387814533084216246887358945009582038577066944158454798150	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1117804358 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1117804358' seed=81172621278267072569387814533084216246887358945009582038577066944158454798150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81172621278267072569387814533084216246887358945009582038577066944158454798150 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_smoke_test uvm_test_seq=edn_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	edn_regwen	12949479630443791285356527242134294548607817611552824844600898163295521687953	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_regwen/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3049081233 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/edn_edn1-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3049081233' seed=12949479630443791285356527242134294548607817611552824844600898163295521687953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12949479630443791285356527242134294548607817611552824844600898163295521687953 --run-dir=/nightly/current_run/scratch/master/edn_edn1-sim-vcs/2.edn_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=edn_regwen_test uvm_test_seq=edn_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126

Simulation Results: edn/edn1

Error Messages