Simulation Results: prim_lfsr

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: vcs [unknown]
Validation stages
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 4 0.00
prim_lfsr_gal_test 0.924s 0.000us 0 1 0.00
prim_lfsr_fib_smoke 0.849s 0.000us 0 1 0.00
prim_lfsr_fib_test 0.862s 0.000us 0 1 0.00
prim_lfsr_gal_smoke 1.536s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 4 test runs
prim_lfsr_gal_test 50441203155217391417965348684596618978779580551307030908335236501683024937891 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv run_dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest run_opts='+prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2530722723 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2530722723' seed=50441203155217391417965348684596618978779580551307030908335236501683024937891 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50441203155217391417965348684596618978779580551307030908335236501683024937891 --run-dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_lfsr_fib_smoke 91003624428416665413202665153887631937593393900244584810233321220958332604439 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv run_dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest run_opts='+prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2752991255 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.2752991255' seed=91003624428416665413202665153887631937593393900244584810233321220958332604439 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91003624428416665413202665153887631937593393900244584810233321220958332604439 --run-dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_lfsr_fib_test 2313760343944071282976823417207071379977432858347527514220852279044916647677 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv run_dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest run_opts='+prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3623098109 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.3623098109' seed=2313760343944071282976823417207071379977432858347527514220852279044916647677 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2313760343944071282976823417207071379977432858347527514220852279044916647677 --run-dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_lfsr_gal_smoke 52328450844965490062983855721819351653157860323355323168199369566078557542586 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv run_dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest run_opts='+prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3291535546 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3291535546' seed=52328450844965490062983855721819351653157860323355323168199369566078557542586 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52328450844965490062983855721819351653157860323355323168199369566078557542586 --run-dir=/nightly/current_run/scratch/master/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job cancelled because all of its dependencies failed or were killed. 1 test run
prim_lfsr None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
prim_lfsr None None