Simulation Results: prim_prince

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: vcs [unknown]
Validation stages
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 10 0.00
prim_prince_test 0.861s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 10 test runs
prim_prince_test 15231573386652458815026935024758295259148300701635250280211421879178873500755 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/0.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=726627411 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_prince_test.726627411' seed=15231573386652458815026935024758295259148300701635250280211421879178873500755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15231573386652458815026935024758295259148300701635250280211421879178873500755 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/0.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_prince_test 50380697662767856027533923214490238581818850841484358314782899502387031586354 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/1.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=660223538 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_prince_test.660223538' seed=50380697662767856027533923214490238581818850841484358314782899502387031586354 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50380697662767856027533923214490238581818850841484358314782899502387031586354 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/1.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_prince_test 110370721900244997009513102730980952292444592636754242143346655255970128329470 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/2.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1660680958 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_prince_test.1660680958' seed=110370721900244997009513102730980952292444592636754242143346655255970128329470 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110370721900244997009513102730980952292444592636754242143346655255970128329470 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/2.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_prince_test 11688395977842925585993731290036915644104325899270008191317371342710215326630 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/3.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=344243110 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_prince_test.344243110' seed=11688395977842925585993731290036915644104325899270008191317371342710215326630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11688395977842925585993731290036915644104325899270008191317371342710215326630 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/3.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_prince_test 13067945688635067429823472934429282157324161487061439802358873814959939782028 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/4.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=884606348 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_prince_test.884606348' seed=13067945688635067429823472934429282157324161487061439802358873814959939782028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13067945688635067429823472934429282157324161487061439802358873814959939782028 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/4.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_prince_test 18973240702348216045206856287511966281238972550246183705375596790166210576478 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/5.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1468629086 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_prince_test.1468629086' seed=18973240702348216045206856287511966281238972550246183705375596790166210576478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18973240702348216045206856287511966281238972550246183705375596790166210576478 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/5.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_prince_test 60710122857598354614907583293896474992062095638554831563585660587029643827661 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/6.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2575997389 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_prince_test.2575997389' seed=60710122857598354614907583293896474992062095638554831563585660587029643827661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60710122857598354614907583293896474992062095638554831563585660587029643827661 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/6.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_prince_test 56751152764714501257060262555256070142893237900456291319745949242095787851144 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/7.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4088151432 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_prince_test.4088151432' seed=56751152764714501257060262555256070142893237900456291319745949242095787851144 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56751152764714501257060262555256070142893237900456291319745949242095787851144 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/7.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_prince_test 14813737436380616593529222378562278714736494495173650058504419615758033098021 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/8.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1457001765 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_prince_test.1457001765' seed=14813737436380616593529222378562278714736494495173650058504419615758033098021 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14813737436380616593529222378562278714736494495173650058504419615758033098021 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/8.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_prince_test 110807401434252911965480529693303103633248323137282041389835383721471869914572 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_prince-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/9.prim_prince_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=617287116 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_prince_test.617287116' seed=110807401434252911965480529693303103633248323137282041389835383721471869914572 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110807401434252911965480529693303103633248323137282041389835383721471869914572 --run-dir=/nightly/current_run/scratch/master/prim_prince-sim-vcs/9.prim_prince_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job cancelled because all of its dependencies failed or were killed. 1 test run
prim_prince None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
prim_prince None None