Simulation Results

Simulation Results: rv_dm/use_dmi_interface

28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]

Validation stages

V1		0.00%
V2		1.11%
V2S		0.00%
V3		0.00%
unmapped		0.00%

0/130 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
smoke				2
	rv_dm_smoke	0.882s	0.000us	2
jtag_dtm_csr_hw_reset				5
	rv_dm_jtag_dtm_csr_hw_reset	0.884s	0.000us	5
jtag_dtm_csr_rw				20
	rv_dm_jtag_dtm_csr_rw	1.626s	0.000us	20
jtag_dtm_csr_bit_bash				5
	rv_dm_jtag_dtm_csr_bit_bash	0.865s	0.000us	5
jtag_dtm_csr_aliasing				5
	rv_dm_jtag_dtm_csr_aliasing	0.865s	0.000us	5
jtag_dmi_csr_hw_reset				5
	rv_dm_jtag_dmi_csr_hw_reset	0.893s	0.000us	5
jtag_dmi_csr_rw				20
	rv_dm_jtag_dmi_csr_rw	1.424s	0.000us	20
jtag_dmi_csr_bit_bash				20
	rv_dm_jtag_dmi_csr_bit_bash	0.902s	0.000us	20
jtag_dmi_csr_aliasing				5
	rv_dm_jtag_dmi_csr_aliasing	0.857s	0.000us	5
jtag_dmi_cmderr_busy				2
	rv_dm_cmderr_busy	0.848s	0.000us	2
jtag_dmi_cmderr_not_supported				2
	rv_dm_cmderr_not_supported	0.848s	0.000us	2
cmderr_exception				2
	rv_dm_cmderr_exception	0.891s	0.000us	2
mem_tl_access_resuming				2
	rv_dm_mem_tl_access_resuming	0.832s	0.000us	2
mem_tl_access_halted				2
	rv_dm_mem_tl_access_halted	0.852s	0.000us	2
cmderr_halt_resume				2
	rv_dm_cmderr_halt_resume	1.559s	0.000us	2
dataaddr_rw_access				2
	rv_dm_dataaddr_rw_access	0.911s	0.000us	2
halt_resume				8
	rv_dm_halt_resume_whereto	1.629s	0.000us	8
progbuf_busy				2
	rv_dm_cmderr_busy	0.848s	0.000us	2
abstractcmd_status				2
	rv_dm_abstractcmd_status	0.851s	0.000us	2
progbuf_read_write_execute				2
	rv_dm_progbuf_read_write_execute	1.519s	0.000us	2
progbuf_exception				2
	rv_dm_cmderr_exception	0.891s	0.000us	2
rom_read_access				2
	rv_dm_rom_read_access	0.843s	0.000us	2
csr_hw_reset				1
	rv_dm_csr_hw_reset	0.861s	0.000us	1
csr_rw				5
	rv_dm_csr_rw	0.878s	0.000us	5
csr_bit_bash				1
	rv_dm_csr_bit_bash	0.855s	0.000us	1
csr_aliasing				1
	rv_dm_csr_aliasing	0.830s	0.000us	1
csr_mem_rw_with_rand_reset				5
	rv_dm_csr_mem_rw_with_rand_reset	0.867s	0.000us	5
regwen_csr_and_corresponding_lockable_csr				6
	rv_dm_csr_aliasing	0.830s	0.000us	1
	rv_dm_csr_rw	0.878s	0.000us	5
mem_walk				1
	rv_dm_mem_walk	0.830s	0.000us	1
mem_partial_access				1
	rv_dm_mem_partial_access	0.844s	0.000us	1

2/180 passed

1.11 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				0	2	0.00
	rv_dm_smoke	0.882s	0.000us	0	2	0.00
jtag_dtm_hard_reset				0	2	0.00
	rv_dm_jtag_dtm_hard_reset	0.856s	0.000us	0	2	0.00
jtag_dtm_idle_hint				0	2	0.00
	rv_dm_jtag_dtm_idle_hint	0.846s	0.000us	0	2	0.00
jtag_dmi_failed_op				0	2	0.00
	rv_dm_dmi_failed_op	0.866s	0.000us	0	2	0.00
jtag_dmi_dm_inactive				0	2	0.00
	rv_dm_jtag_dmi_dm_inactive	1.547s	0.000us	0	2	0.00
sba				0	40	0.00
	rv_dm_sba_tl_access	1.556s	0.000us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	0.905s	0.000us	0	20	0.00
bad_sba				0	20	0.00
	rv_dm_bad_sba_tl_access	1.576s	0.000us	0	20	0.00
sba_autoincrement				0	20	0.00
	rv_dm_autoincr_sba_tl_access	1.375s	0.000us	0	20	0.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	0.831s	0.000us	0	2	0.00
sba_debug_disabled				0	2	0.00
	rv_dm_sba_debug_disabled	0.829s	0.000us	0	2	0.00
ndmreset_req				0	2	0.00
	rv_dm_ndmreset_req	0.838s	0.000us	0	2	0.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	1.523s	0.000us	0	5	0.00
tap_ctrl_transitions				0	11	0.00
	rv_dm_tap_fsm	0.815s	0.000us	0	1	0.00
	rv_dm_tap_fsm_rand_reset	0.891s	0.000us	0	10	0.00
hartsel_warl				0	1	0.00
	rv_dm_hartsel_warl	0.849s	0.000us	0	1	0.00
stress_all				2	20	10.00
	rv_dm_stress_all	10802.000s	0.000us	2	20	10.00
alert_test				0	10	0.00
	rv_dm_alert_test	0.859s	0.000us	0	10	0.00
tl_d_oob_addr_access				0	25	0.00
	rv_dm_tl_errors	1.522s	0.000us	0	25	0.00
tl_d_illegal_access				0	25	0.00
	rv_dm_tl_errors	1.522s	0.000us	0	25	0.00
tl_d_outstanding_access				0	12	0.00
	rv_dm_csr_aliasing	0.830s	0.000us	0	1	0.00
	rv_dm_csr_hw_reset	0.861s	0.000us	0	1	0.00
	rv_dm_csr_rw	0.878s	0.000us	0	5	0.00
	rv_dm_same_csr_outstanding	1.552s	0.000us	0	5	0.00
tl_d_partial_access				0	12	0.00
	rv_dm_csr_aliasing	0.830s	0.000us	0	1	0.00
	rv_dm_csr_hw_reset	0.861s	0.000us	0	1	0.00
	rv_dm_csr_rw	0.878s	0.000us	0	5	0.00
	rv_dm_same_csr_outstanding	1.552s	0.000us	0	5	0.00

V2S

0/50 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
tl_intg_err				30
	rv_dm_sec_cm	1.578s	0.000us	5
	rv_dm_tl_intg_err	1.554s	0.000us	25
sec_cm_bus_integrity				25
	rv_dm_tl_intg_err	1.554s	0.000us	25
sec_cm_lc_hw_debug_en_intersig_mubi				4
	rv_dm_sba_debug_disabled	0.829s	0.000us	2
	rv_dm_debug_disabled	0.849s	0.000us	2
sec_cm_lc_dft_en_intersig_mubi				4
	rv_dm_sba_debug_disabled	0.829s	0.000us	2
	rv_dm_debug_disabled	0.849s	0.000us	2
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2
	rv_dm_smoke	0.882s	0.000us	2
sec_cm_dm_en_ctrl_lc_gated				10
	rv_dm_buffered_enable	0.898s	0.000us	10
sec_cm_sba_tl_lc_gate_fsm_sparse				4
	rv_dm_sparse_lc_gate_fsm	0.879s	0.000us	4
sec_cm_mem_tl_lc_gate_fsm_sparse				4
	rv_dm_sparse_lc_gate_fsm	0.879s	0.000us	4
sec_cm_exec_ctrl_mubi				10
	rv_dm_buffered_enable	0.898s	0.000us	10

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	20	0.00
	rv_dm_stress_all_with_rand_reset	1.546s	0.000us	0	20	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	0.868s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				348 test runs
	rv_dm_csr_aliasing	31632554188758942004361794934294883266356466763245745271612601806339794313887	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_aliasing/latest run_opts='+test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2591335071 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2591335071 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_csr_aliasing.2591335071 -covoverwrite' seed=31632554188758942004361794934294883266356466763245745271612601806339794313887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31632554188758942004361794934294883266356466763245745271612601806339794313887 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_smoke	108207634389423715042464987567316870297487925568260447232481208793292374383215	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2857998959 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_smoke.2857998959 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_smoke.2857998959 -covoverwrite' seed=108207634389423715042464987567316870297487925568260447232481208793292374383215 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108207634389423715042464987567316870297487925568260447232481208793292374383215 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_tap_fsm	43678163745004093937860088453128804004583517799496913267019863224516946006430	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tap_fsm/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=4098199966 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_tap_fsm.4098199966 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_tap_fsm.4098199966 -covoverwrite' seed=43678163745004093937860088453128804004583517799496913267019863224516946006430 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43678163745004093937860088453128804004583517799496913267019863224516946006430 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tap_fsm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_tap_fsm_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_jtag_dtm_csr_hw_reset	2935496760055761753637371022000775689509807058641931492524166111729253845466	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_hw_reset/latest run_opts='+en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1046710746 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1046710746 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dtm_csr_hw_reset.1046710746 -covoverwrite' seed=2935496760055761753637371022000775689509807058641931492524166111729253845466 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2935496760055761753637371022000775689509807058641931492524166111729253845466 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_jtag_dtm_csr_rw	13562403687229824451634777228402506612085312066842728978513066640658147425301	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2870852629 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2870852629 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dtm_csr_rw.2870852629 -covoverwrite' seed=13562403687229824451634777228402506612085312066842728978513066640658147425301 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13562403687229824451634777228402506612085312066842728978513066640658147425301 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_jtag_dtm_csr_bit_bash	100172231198237987126315632782480719966406223745334962800634661805917611535394	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4179930146 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4179930146 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dtm_csr_bit_bash.4179930146 -covoverwrite' seed=100172231198237987126315632782480719966406223745334962800634661805917611535394 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100172231198237987126315632782480719966406223745334962800634661805917611535394 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_jtag_dtm_csr_aliasing	109408384305177799996859289447860758368956743872733230494792634603807631372867	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_aliasing/latest run_opts='+en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1662677571 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1662677571 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dtm_csr_aliasing.1662677571 -covoverwrite' seed=109408384305177799996859289447860758368956743872733230494792634603807631372867 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109408384305177799996859289447860758368956743872733230494792634603807631372867 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_csr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_jtag_dmi_csr_hw_reset	14818129070322768956370203155526171752204489069220681541074618650998461842783	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_hw_reset/latest run_opts='+en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4014622047 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4014622047 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dmi_csr_hw_reset.4014622047 -covoverwrite' seed=14818129070322768956370203155526171752204489069220681541074618650998461842783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14818129070322768956370203155526171752204489069220681541074618650998461842783 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_jtag_dmi_csr_rw	23433163186225842731198646653550653547973863446638869651945219780308203955076	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_rw/latest run_opts='+en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3710083972 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3710083972 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dmi_csr_rw.3710083972 -covoverwrite' seed=23433163186225842731198646653550653547973863446638869651945219780308203955076 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23433163186225842731198646653550653547973863446638869651945219780308203955076 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_jtag_dmi_csr_bit_bash	55977877042368459914077739396979460269243962620118140384600414793761870910371	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_bit_bash/latest run_opts='+en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3451720611 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3451720611 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dmi_csr_bit_bash.3451720611 -covoverwrite' seed=55977877042368459914077739396979460269243962620118140384600414793761870910371 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55977877042368459914077739396979460269243962620118140384600414793761870910371 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_jtag_dmi_csr_aliasing	76835480321072788057825069683113626811391098483094521139535719740281114764768	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_aliasing/latest run_opts='+en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=910075360 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.910075360 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_jtag_dmi_csr_aliasing.910075360 -covoverwrite' seed=76835480321072788057825069683113626811391098483094521139535719740281114764768 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76835480321072788057825069683113626811391098483094521139535719740281114764768 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_csr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_sba_tl_access	110040478614476365939391859636701374092700037196362671853120156789189530088185	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=999289593 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_sba_tl_access.999289593 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_sba_tl_access.999289593 -covoverwrite' seed=110040478614476365939391859636701374092700037196362671853120156789189530088185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110040478614476365939391859636701374092700037196362671853120156789189530088185 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_tl_access_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_delayed_resp_sba_tl_access	2162125529611344131716661238163460641595335208721419524248588892044488579524	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_delayed_resp_sba_tl_access/latest run_opts='+zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2251004356 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2251004356 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_delayed_resp_sba_tl_access.2251004356 -covoverwrite' seed=2162125529611344131716661238163460641595335208721419524248588892044488579524 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2162125529611344131716661238163460641595335208721419524248588892044488579524 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_delayed_resp_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_delayed_resp_sba_tl_access_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_bad_sba_tl_access	25128622909085098625444480889523950281418639233075032999434942834628990451388	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_bad_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1758576316 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_bad_sba_tl_access.1758576316 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_bad_sba_tl_access.1758576316 -covoverwrite' seed=25128622909085098625444480889523950281418639233075032999434942834628990451388 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25128622909085098625444480889523950281418639233075032999434942834628990451388 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_bad_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_bad_sba_tl_access_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_autoincr_sba_tl_access	108851442235874526930625924238117963119546305134562909091198043823635044700740	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_autoincr_sba_tl_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1054020164 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_autoincr_sba_tl_access.1054020164 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_autoincr_sba_tl_access.1054020164 -covoverwrite' seed=108851442235874526930625924238117963119546305134562909091198043823635044700740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108851442235874526930625924238117963119546305134562909091198043823635044700740 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_autoincr_sba_tl_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_autoincr_sba_tl_access_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_tap_fsm_rand_reset	5600314857910583076481030619359718525803378395940022713705842482865216765855	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tap_fsm_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1117601695 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1117601695 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_dm_tap_fsm_rand_reset.1117601695 -covoverwrite' seed=5600314857910583076481030619359718525803378395940022713705842482865216765855 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5600314857910583076481030619359718525803378395940022713705842482865216765855 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_tap_fsm_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_cmderr_busy	28938314962285900743120911343588127258334959195829388090266332995120796828569	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_busy/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2368766873 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_cmderr_busy.2368766873 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_cmderr_busy.2368766873 -covoverwrite' seed=28938314962285900743120911343588127258334959195829388090266332995120796828569 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28938314962285900743120911343588127258334959195829388090266332995120796828569 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_busy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_cmderr_busy_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_cmderr_not_supported	62145028535011319006378507087108017503457541331682053176745701104428352410601	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_not_supported/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2808746985 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_cmderr_not_supported.2808746985 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_cmderr_not_supported.2808746985 -covoverwrite' seed=62145028535011319006378507087108017503457541331682053176745701104428352410601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62145028535011319006378507087108017503457541331682053176745701104428352410601 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_not_supported/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_cmderr_not_supported_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_cmderr_exception	50446413704309246918716582396601784726923152186812173942030279060983704737234	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_exception/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1876710866 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_cmderr_exception.1876710866 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_cmderr_exception.1876710866 -covoverwrite' seed=50446413704309246918716582396601784726923152186812173942030279060983704737234 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50446413704309246918716582396601784726923152186812173942030279060983704737234 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_exception/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_cmderr_exception_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_mem_tl_access_halted	53268811777129531051625354316760781905991938730464846659710902012130611600362	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_tl_access_halted/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1466604522 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_mem_tl_access_halted.1466604522 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_mem_tl_access_halted.1466604522 -covoverwrite' seed=53268811777129531051625354316760781905991938730464846659710902012130611600362 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53268811777129531051625354316760781905991938730464846659710902012130611600362 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_tl_access_halted/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_mem_tl_access_halted_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_mem_tl_access_resuming	80604120596213122576364148641965496702145056829225913464028180869404630325745	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_tl_access_resuming/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=262806001 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_mem_tl_access_resuming.262806001 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_mem_tl_access_resuming.262806001 -covoverwrite' seed=80604120596213122576364148641965496702145056829225913464028180869404630325745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80604120596213122576364148641965496702145056829225913464028180869404630325745 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_mem_tl_access_resuming/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_mem_tl_access_resuming_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_hart_unavail	2393893441059039628241062090848182033344017093909608191038620001222965278369	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_hart_unavail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=694105761 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_hart_unavail.694105761 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_hart_unavail.694105761 -covoverwrite' seed=2393893441059039628241062090848182033344017093909608191038620001222965278369 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2393893441059039628241062090848182033344017093909608191038620001222965278369 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_hart_unavail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_hart_unavail_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_cmderr_halt_resume	4356480580597368573666644760857209111898272452472741914787146893117772043043	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_halt_resume/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1567396643 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_cmderr_halt_resume.1567396643 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_cmderr_halt_resume.1567396643 -covoverwrite' seed=4356480580597368573666644760857209111898272452472741914787146893117772043043 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4356480580597368573666644760857209111898272452472741914787146893117772043043 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_cmderr_halt_resume/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_cmderr_halt_resume_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_dataaddr_rw_access	65320972746811724052751726634928940015096095462396707607747307483116147997154	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_dataaddr_rw_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=697989602 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_dataaddr_rw_access.697989602 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_dataaddr_rw_access.697989602 -covoverwrite' seed=65320972746811724052751726634928940015096095462396707607747307483116147997154 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65320972746811724052751726634928940015096095462396707607747307483116147997154 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_dataaddr_rw_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_dataaddr_rw_access_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_halt_resume_whereto	95838196194224806589520242608833328592493777841036884285000094415957876988994	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_halt_resume_whereto/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3934444610 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_halt_resume_whereto.3934444610 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_halt_resume_whereto.3934444610 -covoverwrite' seed=95838196194224806589520242608833328592493777841036884285000094415957876988994 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95838196194224806589520242608833328592493777841036884285000094415957876988994 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_halt_resume_whereto/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_halt_resume_whereto_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_sba_debug_disabled	18071373785554851175194026601718984634473290365006851737192452589554957531280	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sba_debug_disabled/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3169564816 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_sba_debug_disabled.3169564816 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_sba_debug_disabled.3169564816 -covoverwrite' seed=18071373785554851175194026601718984634473290365006851737192452589554957531280 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18071373785554851175194026601718984634473290365006851737192452589554957531280 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sba_debug_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sba_debug_disabled_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_ndmreset_req	44887875625970874806801668804026660786766003379561358144877367412505419080276	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_ndmreset_req/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=421421652 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_ndmreset_req.421421652 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_ndmreset_req.421421652 -covoverwrite' seed=44887875625970874806801668804026660786766003379561358144877367412505419080276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44887875625970874806801668804026660786766003379561358144877367412505419080276 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_ndmreset_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_ndmreset_req_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_jtag_dtm_idle_hint	87997714428859155603969929938937249160257396694324245892972938342505017023996	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_idle_hint/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3814759932 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3814759932 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_jtag_dtm_idle_hint.3814759932 -covoverwrite' seed=87997714428859155603969929938937249160257396694324245892972938342505017023996 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87997714428859155603969929938937249160257396694324245892972938342505017023996 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_idle_hint/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_idle_hint_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_jtag_dmi_dm_inactive	7867286515717415157757760357046252018460314343937047267755361534065419201186	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_dm_inactive/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2068818594 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2068818594 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_jtag_dmi_dm_inactive.2068818594 -covoverwrite' seed=7867286515717415157757760357046252018460314343937047267755361534065419201186 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7867286515717415157757760357046252018460314343937047267755361534065419201186 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_dm_inactive/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_dm_inactive_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_jtag_dmi_debug_disabled	14396016713429673900620029901041477974103046535535255791068527891466359203902	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_debug_disabled/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=842852414 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.842852414 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_jtag_dmi_debug_disabled.842852414 -covoverwrite' seed=14396016713429673900620029901041477974103046535535255791068527891466359203902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14396016713429673900620029901041477974103046535535255791068527891466359203902 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dmi_debug_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dmi_debug_disabled_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_jtag_dtm_hard_reset	806257941022536882854238099720756736531968919961248136524618959550835704129	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_hard_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=597016897 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_jtag_dtm_hard_reset.597016897 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_jtag_dtm_hard_reset.597016897 -covoverwrite' seed=806257941022536882854238099720756736531968919961248136524618959550835704129 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=806257941022536882854238099720756736531968919961248136524618959550835704129 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_jtag_dtm_hard_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_jtag_dtm_hard_reset_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_abstractcmd_status	9219808754384739610028068044057717244736521581635688571667559387593989482414	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_abstractcmd_status/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2817320878 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_abstractcmd_status.2817320878 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_abstractcmd_status.2817320878 -covoverwrite' seed=9219808754384739610028068044057717244736521581635688571667559387593989482414 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9219808754384739610028068044057717244736521581635688571667559387593989482414 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_abstractcmd_status/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_abstractcmd_status_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_rom_read_access	43634308883098042133545061399584099273153177221978087130688496377486253460147	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_rom_read_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3483601587 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_rom_read_access.3483601587 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_rom_read_access.3483601587 -covoverwrite' seed=43634308883098042133545061399584099273153177221978087130688496377486253460147 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43634308883098042133545061399584099273153177221978087130688496377486253460147 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_rom_read_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_rom_read_access_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_progbuf_read_write_execute	69326484050364525360845091791100743144692370513580405680577417690559066007985	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_progbuf_read_write_execute/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3985500593 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_progbuf_read_write_execute.3985500593 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_progbuf_read_write_execute.3985500593 -covoverwrite' seed=69326484050364525360845091791100743144692370513580405680577417690559066007985 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69326484050364525360845091791100743144692370513580405680577417690559066007985 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_progbuf_read_write_execute/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_progbuf_read_write_execute_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_debug_disabled	62347550787187915089632325250156274900383476436804007648420894448572362735786	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_debug_disabled/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=4254679210 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_debug_disabled.4254679210 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_debug_disabled.4254679210 -covoverwrite' seed=62347550787187915089632325250156274900383476436804007648420894448572362735786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62347550787187915089632325250156274900383476436804007648420894448572362735786 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_debug_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_debug_disabled_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_dmi_failed_op	86443000477291975173120240974395470440143090338561170855721772500239516121185	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_dmi_failed_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=3360110689 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_dmi_failed_op.3360110689 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_dmi_failed_op.3360110689 -covoverwrite' seed=86443000477291975173120240974395470440143090338561170855721772500239516121185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86443000477291975173120240974395470440143090338561170855721772500239516121185 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_dmi_failed_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_dmi_failed_op_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_hartsel_warl	67514027591896222294610745421545324311686648607997090805940086532872564081282	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_hartsel_warl/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=4242768514 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_hartsel_warl.4242768514 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_hartsel_warl.4242768514 -covoverwrite' seed=67514027591896222294610745421545324311686648607997090805940086532872564081282 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67514027591896222294610745421545324311686648607997090805940086532872564081282 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_hartsel_warl/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_hartsel_warl_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_buffered_enable	106384818791000223639253356937489688559581112749641358242856137276573383344487	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_buffered_enable/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=1746878823 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_buffered_enable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_buffered_enable.1746878823 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_buffered_enable.1746878823 -covoverwrite' seed=106384818791000223639253356937489688559581112749641358242856137276573383344487 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106384818791000223639253356937489688559581112749641358242856137276573383344487 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_buffered_enable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_buffered_enable_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	rv_dm_sparse_lc_gate_fsm	48510933441186654772182484276024770834690245923847971775708848488487010732260	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sparse_lc_gate_fsm/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/xcelium.d -r tb +SVSEED=2050525412 +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sparse_lc_gate_fsm_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage/default/0.rv_dm_sparse_lc_gate_fsm.2050525412 -covworkdir /nightly/current_run/scratch/master/rv_dm-sim-xcelium/coverage -covscope default -covtest 0.rv_dm_sparse_lc_gate_fsm.2050525412 -covoverwrite' seed=48510933441186654772182484276024770834690245923847971775708848488487010732260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48510933441186654772182484276024770834690245923847971775708848488487010732260 --run-dir=/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_sparse_lc_gate_fsm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_dm_base_test uvm_test_seq=rv_dm_sparse_lc_gate_fsm_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126