Simulation Results

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
xbar_smoke	0	20	0.00
	xbar_smoke	1.541s	0.000us	0	20	0.00

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
xbar_base_random_sequence	0	20	0.00
	xbar_random	1.514s	0.000us	0	20	0.00
xbar_random_delay	0	120	0.00
	xbar_smoke_zero_delays	0.910s	0.000us	0	20	0.00
	xbar_smoke_large_delays	1.595s	0.000us	0	20	0.00
	xbar_smoke_slow_rsp	1.535s	0.000us	0	20	0.00
	xbar_random_zero_delays	1.534s	0.000us	0	20	0.00
	xbar_random_large_delays	1.538s	0.000us	0	20	0.00
	xbar_random_slow_rsp	1.569s	0.000us	0	20	0.00
xbar_unmapped_address	0	40	0.00
	xbar_unmapped_addr	1.530s	0.000us	0	20	0.00
	xbar_error_and_unmapped_addr	1.573s	0.000us	0	20	0.00
xbar_error_cases	0	40	0.00
	xbar_error_random	2.102s	0.000us	0	20	0.00
	xbar_error_and_unmapped_addr	1.573s	0.000us	0	20	0.00
xbar_all_access_same_device	0	70	0.00
	xbar_access_same_device	1.407s	0.000us	0	20	0.00
	xbar_access_same_device_slow_rsp	2.443s	0.000us	0	50	0.00
xbar_all_hosts_use_same_source_id	0	20	0.00
	xbar_same_source	1.370s	0.000us	0	20	0.00
xbar_stress_all	0	70	0.00
	xbar_stress_all	1.534s	0.000us	0	20	0.00
	xbar_stress_all_with_error	1.748s	0.000us	0	50	0.00
xbar_stress_with_reset	0	70	0.00
	xbar_stress_all_with_rand_reset	2.140s	0.000us	0	20	0.00
	xbar_stress_all_with_reset_error	1.576s	0.000us	0	50	0.00

Error Messages

V1		0.00%
V2		0.00%

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				450 test runs
	xbar_smoke	25845266437675527906999430806679580586693961763639228623442312420062393305819	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1034980059 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1034980059' seed=25845266437675527906999430806679580586693961763639228623442312420062393305819 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25845266437675527906999430806679580586693961763639228623442312420062393305819 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_smoke_zero_delays	99802627436079825029858119455680775731930725757651227535607758899076838625016	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2832371448 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2832371448' seed=99802627436079825029858119455680775731930725757651227535607758899076838625016 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99802627436079825029858119455680775731930725757651227535607758899076838625016 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_smoke_large_delays	49709646977738158391590323260082614641417938850805560948428511493906799669273	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=121778201 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.121778201' seed=49709646977738158391590323260082614641417938850805560948428511493906799669273 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49709646977738158391590323260082614641417938850805560948428511493906799669273 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_smoke_slow_rsp	14162037706993062276316358928408433090351106909372441215357875828797941693024	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3778230880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3778230880' seed=14162037706993062276316358928408433090351106909372441215357875828797941693024 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14162037706993062276316358928408433090351106909372441215357875828797941693024 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_random	90122564233005879044897819898960007498994869580010998817201380737759841127424	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1342999552 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1342999552' seed=90122564233005879044897819898960007498994869580010998817201380737759841127424 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90122564233005879044897819898960007498994869580010998817201380737759841127424 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_random_zero_delays	48925922107634702181979889693083292069024072260761314507242950396297880058868	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=140819444 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.140819444' seed=48925922107634702181979889693083292069024072260761314507242950396297880058868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48925922107634702181979889693083292069024072260761314507242950396297880058868 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_random_large_delays	42672089598313615220839001028019855480745145649508072216780457297421721848432	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3458124400 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3458124400' seed=42672089598313615220839001028019855480745145649508072216780457297421721848432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42672089598313615220839001028019855480745145649508072216780457297421721848432 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_random_slow_rsp	27553187483554586404662370295020458718825969253386032769379254335085184854424	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1443408280 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1443408280' seed=27553187483554586404662370295020458718825969253386032769379254335085184854424 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27553187483554586404662370295020458718825969253386032769379254335085184854424 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_access_same_device	89123296005383522531367686352861868430251479192520767628137733762554372479451	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=652138971 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.652138971' seed=89123296005383522531367686352861868430251479192520767628137733762554372479451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89123296005383522531367686352861868430251479192520767628137733762554372479451 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_access_same_device_slow_rsp	62346437611228733321473091373582294657838039374897618783929458600431729232553	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=575916713 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.575916713' seed=62346437611228733321473091373582294657838039374897618783929458600431729232553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62346437611228733321473091373582294657838039374897618783929458600431729232553 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_same_source	72125940074079450894399920024199355788948537997693872379098507348270919531331	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3568909123 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3568909123' seed=72125940074079450894399920024199355788948537997693872379098507348270919531331 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72125940074079450894399920024199355788948537997693872379098507348270919531331 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_error_random	56780605335694129845929005075098246876639586434134547529312788424978720672000	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1110493440 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1110493440' seed=56780605335694129845929005075098246876639586434134547529312788424978720672000 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56780605335694129845929005075098246876639586434134547529312788424978720672000 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_unmapped_addr	107444315127683527182342015841799207160335543841124834343018884208866945882078	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3438761950 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3438761950' seed=107444315127683527182342015841799207160335543841124834343018884208866945882078 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107444315127683527182342015841799207160335543841124834343018884208866945882078 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_error_and_unmapped_addr	113542641314299286695346350777240127578573043399117124093057617431797523311628	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3184290828 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3184290828' seed=113542641314299286695346350777240127578573043399117124093057617431797523311628 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113542641314299286695346350777240127578573043399117124093057617431797523311628 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_stress_all	73005140573377446424393608017817932829220763705328947558383269842211247886837	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2100433397 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2100433397' seed=73005140573377446424393608017817932829220763705328947558383269842211247886837 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73005140573377446424393608017817932829220763705328947558383269842211247886837 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_stress_all_with_rand_reset	10526826253445922968797033598991084829305080568662245512347889398584244430803	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4281067475 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.4281067475' seed=10526826253445922968797033598991084829305080568662245512347889398584244430803 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10526826253445922968797033598991084829305080568662245512347889398584244430803 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_stress_all_with_error	73089280301715291446511742797285115800329952518018947816257870695570508624050	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=672149682 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.672149682' seed=73089280301715291446511742797285115800329952518018947816257870695570508624050 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73089280301715291446511742797285115800329952518018947816257870695570508624050 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_stress_all_with_reset_error	108286958393929342068841569031359242517443237604322232531062629710611580131281	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=178198481 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.178198481' seed=108286958393929342068841569031359242517443237604322232531062629710611580131281 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108286958393929342068841569031359242517443237604322232531062629710611580131281 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_smoke	66679458521535303140490137511013149174052910860913498335395473722995890272321	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1084569665 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1084569665' seed=66679458521535303140490137511013149174052910860913498335395473722995890272321 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66679458521535303140490137511013149174052910860913498335395473722995890272321 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_smoke_zero_delays	931096252873204573309749688031358516689001210120669005310878117302279567619	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3132586243 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3132586243' seed=931096252873204573309749688031358516689001210120669005310878117302279567619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=931096252873204573309749688031358516689001210120669005310878117302279567619 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_smoke_large_delays	55899685690130040697533023728661384580579975923655729694910253585212825927537	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2936012657 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2936012657' seed=55899685690130040697533023728661384580579975923655729694910253585212825927537 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55899685690130040697533023728661384580579975923655729694910253585212825927537 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_smoke_slow_rsp	86957037934905728131113686522182156613286741275530454149246295727565327452384	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1692027104 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1692027104' seed=86957037934905728131113686522182156613286741275530454149246295727565327452384 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86957037934905728131113686522182156613286741275530454149246295727565327452384 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_random	70799741012067061404682408551618579614558313094020725571738480798455087155426	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1982777570 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1982777570' seed=70799741012067061404682408551618579614558313094020725571738480798455087155426 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70799741012067061404682408551618579614558313094020725571738480798455087155426 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_random_zero_delays	21383674567024204369917681339156435797396171462943940182517326924688067880548	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=592143972 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.592143972' seed=21383674567024204369917681339156435797396171462943940182517326924688067880548 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21383674567024204369917681339156435797396171462943940182517326924688067880548 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_random_large_delays	10569941435417898903534935499677897280945964201289400604942526194571917219146	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3377812810 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3377812810' seed=10569941435417898903534935499677897280945964201289400604942526194571917219146 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10569941435417898903534935499677897280945964201289400604942526194571917219146 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_random_slow_rsp	58890138514625953213383557249985359353981029352696759344339770782504713152053	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2549048885 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2549048885' seed=58890138514625953213383557249985359353981029352696759344339770782504713152053 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58890138514625953213383557249985359353981029352696759344339770782504713152053 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_access_same_device	43155468213041022401913410285129798369184967532327362560881285400766085992766	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=542249278 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.542249278' seed=43155468213041022401913410285129798369184967532327362560881285400766085992766 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43155468213041022401913410285129798369184967532327362560881285400766085992766 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_access_same_device_slow_rsp	87838290137704465252677641599723917306725119741990000726749138970156745074446	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2491393806 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.2491393806' seed=87838290137704465252677641599723917306725119741990000726749138970156745074446 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87838290137704465252677641599723917306725119741990000726749138970156745074446 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_same_source	8594070717176412852504936857883683135399923281800417548777386735107663092901	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=678583461 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.678583461' seed=8594070717176412852504936857883683135399923281800417548777386735107663092901 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8594070717176412852504936857883683135399923281800417548777386735107663092901 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_error_random	27022627244191650766177233942047707971662518847852486475238404095943466742699	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3579507627 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3579507627' seed=27022627244191650766177233942047707971662518847852486475238404095943466742699 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27022627244191650766177233942047707971662518847852486475238404095943466742699 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_unmapped_addr	98771615560045371062088925293535871868501849872455585669046911838894777642289	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3836947761 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3836947761' seed=98771615560045371062088925293535871868501849872455585669046911838894777642289 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98771615560045371062088925293535871868501849872455585669046911838894777642289 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_error_and_unmapped_addr	61472951217951943339581291050250013492472342201754749410173122404915626096823	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2457581751 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2457581751' seed=61472951217951943339581291050250013492472342201754749410173122404915626096823 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61472951217951943339581291050250013492472342201754749410173122404915626096823 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_stress_all	9555262995324950054687916096218385580834831720480559979915446494349470050102	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4256016182 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.4256016182' seed=9555262995324950054687916096218385580834831720480559979915446494349470050102 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9555262995324950054687916096218385580834831720480559979915446494349470050102 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_stress_all_with_rand_reset	9148260364230587032017461838345953024501744996904367712922273325793408314982	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2184572518 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.2184572518' seed=9148260364230587032017461838345953024501744996904367712922273325793408314982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9148260364230587032017461838345953024501744996904367712922273325793408314982 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_stress_all_with_error	4624043866665939471249573127049037236067875866504970215610975492870376278717	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39602877 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.39602877' seed=4624043866665939471249573127049037236067875866504970215610975492870376278717 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4624043866665939471249573127049037236067875866504970215610975492870376278717 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_stress_all_with_reset_error	113700266311691691827089995098930283810463976604507608935827100768528895709678	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=600445422 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.600445422' seed=113700266311691691827089995098930283810463976604507608935827100768528895709678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113700266311691691827089995098930283810463976604507608935827100768528895709678 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_smoke	111568329064043100183948113893391628427309153944510820685062868617995588333070	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=551939598 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.551939598' seed=111568329064043100183948113893391628427309153944510820685062868617995588333070 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111568329064043100183948113893391628427309153944510820685062868617995588333070 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_smoke_zero_delays	103674201963625835436245426973189723208814247441166707555054737800376029285677	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3076001069 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3076001069' seed=103674201963625835436245426973189723208814247441166707555054737800376029285677 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103674201963625835436245426973189723208814247441166707555054737800376029285677 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	xbar_smoke_large_delays	9165588602478565866940913664012973229810394510806438172347026517095495852924	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1200448380 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1200448380' seed=9165588602478565866940913664012973229810394510806438172347026517095495852924 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9165588602478565866940913664012973229810394510806438172347026517095495852924 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126

Simulation Results: xbar_peri

Error Messages