Simulation Results: rom_ctrl/64kb

 
18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.29 %
  • code
  • 88.90 %
  • assert
  • 97.67 %
  • func
  • 99.29 %
  • block
  • 89.61 %
  • line
  • 91.66 %
  • branch
  • 83.95 %
  • toggle
  • 84.74 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 5.000s 383.571us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 99.173us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 3.000s 71.781us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 264.648us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 61.507us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 63.808us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 3.000s 71.781us 5 5 100.00
rom_ctrl_csr_aliasing 4.000s 61.507us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 74.881us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 68.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 6.000s 354.359us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 16.000s 1430.202us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 9.000s 713.895us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 3.000s 54.218us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 9.000s 380.633us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 9.000s 380.633us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.000s 99.173us 1 1 100.00
rom_ctrl_csr_rw 3.000s 71.781us 5 5 100.00
rom_ctrl_csr_aliasing 4.000s 61.507us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 86.335us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.000s 99.173us 1 1 100.00
rom_ctrl_csr_rw 3.000s 71.781us 5 5 100.00
rom_ctrl_csr_aliasing 4.000s 61.507us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 86.335us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 97.000s 44754.194us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.000s 8395.801us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 267.000s 1703.171us 5 5 100.00
rom_ctrl_tl_intg_err 64.000s 200.258us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 267.000s 1703.171us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 267.000s 1703.171us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 97.000s 44754.194us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 97.000s 44754.194us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 97.000s 44754.194us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 97.000s 44754.194us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 97.000s 44754.194us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 267.000s 1703.171us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 267.000s 1703.171us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 5.000s 383.571us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 5.000s 383.571us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 5.000s 383.571us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 64.000s 200.258us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 97.000s 44754.194us 20 20 100.00
rom_ctrl_kmac_err_chk 9.000s 713.895us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 97.000s 44754.194us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 97.000s 44754.194us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 97.000s 44754.194us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.000s 8395.801us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 267.000s 1703.171us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 12 20 60.00
rom_ctrl_stress_all_with_rand_reset 56.000s 7422.491us 12 20 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:480) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 6 test runs
rom_ctrl_stress_all_with_rand_reset 70266472718611714170775893611410988234434301958818277026100473652031216073853 124
UVM_INFO @ 3318645653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 87319515220272441758459306639102147821897571312954743755901698135546007493307 90
UVM_INFO @ 250947985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 3178923840597706113256478457077287368594128934053127709629347588709818620858 107
UVM_INFO @ 13202748214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 55300256725698503610401027536358364466453401362302305957839473576699342446070 91
UVM_INFO @ 745269424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 106593238294167039001040501483401204719270420033890608095265238097043617248739 131
UVM_INFO @ 6110126021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 84479924398115791889335886756736568214670729079154618570021893562620231091332 109
UVM_INFO @ 5104728139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 81919976777698769424062365907658098229797301435687799875733326058006429976167 88
UVM_INFO @ 333597786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 91397644912217785436826657805543529714273629070712343819231172258397067635776 88
UVM_INFO @ 354358633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:354) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 2 test runs
rom_ctrl_stress_all_with_rand_reset 96041887884612492830287471565855901923611873638318611798966283604754962747311 110
UVM_INFO @ 899453241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 58595674889407973209784613078504670299295409802041364669055219768789624448226 124
UVM_INFO @ 12095896179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---