Simulation Results: adc_ctrl

 
22/03/2026 00:11:46 DVSim: v1.16.0 sha: 2a81083 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.07 %
  • code
  • 98.08 %
  • assert
  • 95.95 %
  • func
  • 19.19 %
  • line
  • 99.05 %
  • branch
  • 97.77 %
  • cond
  • 93.59 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.21%
V2S
100.00%
V3
98.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
adc_ctrl_smoke 21.320s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
adc_ctrl_csr_hw_reset 3.130s 0.000us 5 5 100.00
csr_rw 20 20 100.00
adc_ctrl_csr_rw 2.760s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
adc_ctrl_csr_bit_bash 145.140s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
adc_ctrl_csr_aliasing 4.060s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.770s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
adc_ctrl_csr_rw 2.760s 0.000us 20 20 100.00
adc_ctrl_csr_aliasing 4.060s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 50 50 100.00
adc_ctrl_filters_polled 1124.260s 0.000us 50 50 100.00
filters_polled_fixed 50 50 100.00
adc_ctrl_filters_polled_fixed 1446.630s 0.000us 50 50 100.00
filters_interrupt 50 50 100.00
adc_ctrl_filters_interrupt 1176.920s 0.000us 50 50 100.00
filters_interrupt_fixed 50 50 100.00
adc_ctrl_filters_interrupt_fixed 1314.890s 0.000us 50 50 100.00
filters_wakeup 50 50 100.00
adc_ctrl_filters_wakeup 1496.040s 0.000us 50 50 100.00
filters_wakeup_fixed 50 50 100.00
adc_ctrl_filters_wakeup_fixed 1554.590s 0.000us 50 50 100.00
filters_both 50 50 100.00
adc_ctrl_filters_both 1421.900s 0.000us 50 50 100.00
clock_gating 36 50 72.00
adc_ctrl_clock_gating 1662.850s 0.000us 36 50 72.00
poweron_counter 50 50 100.00
adc_ctrl_poweron_counter 19.290s 0.000us 50 50 100.00
lowpower_counter 50 50 100.00
adc_ctrl_lowpower_counter 128.200s 0.000us 50 50 100.00
fsm_reset 50 50 100.00
adc_ctrl_fsm_reset 327.940s 0.000us 50 50 100.00
stress_all 49 50 98.00
adc_ctrl_stress_all 4139.910s 0.000us 49 50 98.00
alert_test 50 50 100.00
adc_ctrl_alert_test 2.330s 0.000us 50 50 100.00
intr_test 50 50 100.00
adc_ctrl_intr_test 2.330s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
adc_ctrl_tl_errors 3.830s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
adc_ctrl_tl_errors 3.830s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
adc_ctrl_csr_hw_reset 3.130s 0.000us 5 5 100.00
adc_ctrl_csr_rw 2.760s 0.000us 20 20 100.00
adc_ctrl_csr_aliasing 4.060s 0.000us 5 5 100.00
adc_ctrl_same_csr_outstanding 22.510s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
adc_ctrl_csr_hw_reset 3.130s 0.000us 5 5 100.00
adc_ctrl_csr_rw 2.760s 0.000us 20 20 100.00
adc_ctrl_csr_aliasing 4.060s 0.000us 5 5 100.00
adc_ctrl_same_csr_outstanding 22.510s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
adc_ctrl_sec_cm 12.680s 0.000us 5 5 100.00
adc_ctrl_tl_intg_err 20.840s 0.000us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
adc_ctrl_tl_intg_err 20.840s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 49 50 98.00
adc_ctrl_stress_all_with_rand_reset 19.510s 0.000us 49 50 98.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
adc_ctrl_clock_gating 107722345672012495193632313856211592498357047815743747695398116218762294868988 334
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 100913747707670421376885500060982623192027186868008044944097117158238730406270 351
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 32575952544210805816121717540196866756760803562104302401499460783867318958634 351
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 23932762973362614050869444334667291480525702296219394139451053416295629756529 351
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 49917061448511090425965490493769602788031795175288743248972262622042085804121 334
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
adc_ctrl_clock_gating 28962709314322086732555850226889067043709568486570841225466203118392047614081 317
UVM_ERROR @ 1681462346 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 1681462346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 67518232317425793033424764956362874363160454045287892379463044840769063225092 334
UVM_ERROR @ 204255554712 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 204255554712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 41355937898791576339303536104881059374287512904656367977242292543271046586620 337
UVM_ERROR @ 1672736192 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 1672736192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 82490988517346629123441018376583846018760078795249995999416850094048164151528 317
UVM_ERROR @ 1533567043 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 1533567043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 6852996096956210789490110438790428386281884323872198036237535744774191499148 336
UVM_ERROR @ 170266087195 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 170266087195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 55255460403462752400498454927538455194812017460013813527512852055028782729869 317
UVM_ERROR @ 1980685976 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 1980685976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 30029395136327729544462281031900142409059197646288303348724086349235159830265 351
UVM_ERROR @ 395787742130 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 395787742130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 4965219221292827196064487345421005103288780210651317777881375450958220959932 351
UVM_ERROR @ 326814795156 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 326814795156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 84652825777165479200716800902284381995491071633670571261127129381269903592072 334
UVM_ERROR @ 179569110241 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 179569110241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 101783217443681340353356389263282768059153846455015242631542539684549132346653 317
UVM_ERROR @ 2672626105 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 2672626105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 83832988762994968722188338017991797948129451200563137033009048750894257435537 334
UVM_ERROR @ 167652858094 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 167652858094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---