Simulation Results

Simulation Results: clkmgr

22/03/2026 00:11:46 DVSim: v1.16.0 sha: 2a81083 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
94.41 %

code
98.95 %

assert
96.47 %

func
87.82 %

line
99.34 %

branch
99.17 %

cond
96.22 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		98.12%
V3		99.00%

130/130 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	clkmgr_smoke	1.150s	0.000us	50	50	100.00
csr_hw_reset				5	5	100.00
	clkmgr_csr_hw_reset	0.930s	0.000us	5	5	100.00
csr_rw				20	20	100.00
	clkmgr_csr_rw	1.140s	0.000us	20	20	100.00
csr_bit_bash				5	5	100.00
	clkmgr_csr_bit_bash	11.540s	0.000us	5	5	100.00
csr_aliasing				5	5	100.00
	clkmgr_csr_aliasing	1.830s	0.000us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	clkmgr_csr_mem_rw_with_rand_reset	2.080s	0.000us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	clkmgr_csr_rw	1.140s	0.000us	20	20	100.00
	clkmgr_csr_aliasing	1.830s	0.000us	5	5	100.00

640/640 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				50	50	100.00
	clkmgr_peri	1.090s	0.000us	50	50	100.00
trans_enables				50	50	100.00
	clkmgr_trans	1.500s	0.000us	50	50	100.00
extclk				50	50	100.00
	clkmgr_extclk	1.200s	0.000us	50	50	100.00
clk_status				50	50	100.00
	clkmgr_clk_status	0.970s	0.000us	50	50	100.00
jitter				50	50	100.00
	clkmgr_smoke	1.150s	0.000us	50	50	100.00
frequency				50	50	100.00
	clkmgr_frequency	14.020s	0.000us	50	50	100.00
frequency_timeout				50	50	100.00
	clkmgr_frequency_timeout	11.170s	0.000us	50	50	100.00
frequency_overflow				50	50	100.00
	clkmgr_frequency	14.020s	0.000us	50	50	100.00
stress_all				50	50	100.00
	clkmgr_stress_all	35.940s	0.000us	50	50	100.00
alert_test				50	50	100.00
	clkmgr_alert_test	1.920s	0.000us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	clkmgr_tl_errors	3.430s	0.000us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	clkmgr_tl_errors	3.430s	0.000us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	clkmgr_csr_hw_reset	0.930s	0.000us	5	5	100.00
	clkmgr_csr_rw	1.140s	0.000us	20	20	100.00
	clkmgr_csr_aliasing	1.830s	0.000us	5	5	100.00
	clkmgr_same_csr_outstanding	2.270s	0.000us	20	20	100.00
tl_d_partial_access				50	50	100.00
	clkmgr_csr_hw_reset	0.930s	0.000us	5	5	100.00
	clkmgr_csr_rw	1.140s	0.000us	20	20	100.00
	clkmgr_csr_aliasing	1.830s	0.000us	5	5	100.00
	clkmgr_same_csr_outstanding	2.270s	0.000us	20	20	100.00

V2S

574/585 passed

98.12 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				22	25	88.00
	clkmgr_tl_intg_err	9.880s	0.000us	20	20	100.00
	clkmgr_sec_cm	3.030s	0.000us	2	5	40.00
shadow_reg_update_error				20	20	100.00
	clkmgr_shadow_reg_errors	3.240s	0.000us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	clkmgr_shadow_reg_errors	3.240s	0.000us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	clkmgr_shadow_reg_errors	3.240s	0.000us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	clkmgr_shadow_reg_errors	3.240s	0.000us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	clkmgr_shadow_reg_errors_with_csr_rw	3.480s	0.000us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	clkmgr_tl_intg_err	9.880s	0.000us	20	20	100.00
sec_cm_meas_clk_bkgn_chk				50	50	100.00
	clkmgr_frequency	14.020s	0.000us	50	50	100.00
sec_cm_timeout_clk_bkgn_chk				50	50	100.00
	clkmgr_frequency_timeout	11.170s	0.000us	50	50	100.00
sec_cm_meas_config_shadow				20	20	100.00
	clkmgr_shadow_reg_errors	3.240s	0.000us	20	20	100.00
sec_cm_idle_intersig_mubi				50	50	100.00
	clkmgr_idle_intersig_mubi	1.670s	0.000us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				50	50	100.00
	clkmgr_lc_ctrl_intersig_mubi	1.770s	0.000us	50	50	100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi				50	50	100.00
	clkmgr_lc_clk_byp_req_intersig_mubi	1.300s	0.000us	50	50	100.00
sec_cm_clk_handshake_intersig_mubi				48	50	96.00
	clkmgr_clk_handshake_intersig_mubi	1.150s	0.000us	48	50	96.00
sec_cm_div_intersig_mubi				50	50	100.00
	clkmgr_div_intersig_mubi	1.400s	0.000us	50	50	100.00
sec_cm_jitter_config_mubi				20	20	100.00
	clkmgr_csr_rw	1.140s	0.000us	20	20	100.00
sec_cm_idle_ctr_redun				2	5	40.00
	clkmgr_sec_cm	3.030s	0.000us	2	5	40.00
sec_cm_meas_config_regwen				20	20	100.00
	clkmgr_csr_rw	1.140s	0.000us	20	20	100.00
sec_cm_clk_ctrl_config_regwen				20	20	100.00
	clkmgr_csr_rw	1.140s	0.000us	20	20	100.00
prim_count_check				2	5	40.00
	clkmgr_sec_cm	3.030s	0.000us	2	5	40.00

99/100 passed

99.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				50	50	100.00
	clkmgr_regwen	4.640s	0.000us	50	50	100.00
stress_all_with_rand_reset				49	50	98.00
	clkmgr_stress_all_with_rand_reset	127.170s	0.000us	49	50	98.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
	clkmgr_sec_cm	26047544083498945268168244427228842722347825285993028552109581540856660485040	94	UVM_ERROR @ 21760714 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 21760714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	115382598454753475611760638480665436416693931182509808284268783154420710160495	99	UVM_ERROR @ 49449345 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 49449345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	58883759579895461069214775510288047193475750349467036772476804320061177028160	128	UVM_ERROR @ 184477563 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 184477563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [] vs [*]) extclk_status mismatch
	clkmgr_clk_handshake_intersig_mubi	59673607478441673210975584852756351268924467460311347945915712861976232907	74	UVM_ERROR @ 6850631 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (11 [0xb] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 6850631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_clk_handshake_intersig_mubi	50813678410120079386477214679830348243665930885757983357386641317263232571457	74	UVM_ERROR @ 8156472 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (7 [0x7] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 8156472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(lc_clk_byp_req \|\| (io_clk_byp_req_o != MuBi4False))'
	clkmgr_stress_all_with_rand_reset	19299780829180967875693102063231427368765273881447420814223441257138078936977	103	Offending '(lc_clk_byp_req \|\| (io_clk_byp_req_o != MuBi4False))' UVM_ERROR @ 90210182 ps: (clkmgr_extclk_sva_if.sv:41) [ASSERT FAILED] IoClkBypReqFall_A UVM_INFO @ 90210182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---