Simulation Results: keymgr

 
22/03/2026 00:11:46 DVSim: v1.16.0 sha: 2a81083 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.78 %
  • code
  • 98.45 %
  • assert
  • 97.72 %
  • func
  • 91.18 %
  • line
  • 99.17 %
  • branch
  • 98.92 %
  • cond
  • 98.03 %
  • toggle
  • 98.48 %
  • FSM
  • 97.67 %
Validation stages
V1
100.00%
V2
99.52%
V2S
100.00%
V3
62.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 26.960s 0.000us 50 50 100.00
random 50 50 100.00
keymgr_random 54.840s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.420s 0.000us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.800s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 11.100s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 12.210s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.790s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.800s 0.000us 20 20 100.00
keymgr_csr_aliasing 12.210s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 84.630s 0.000us 50 50 100.00
sideload 199 200 99.50
keymgr_sideload 34.560s 0.000us 49 50 98.00
keymgr_sideload_kmac 49.990s 0.000us 50 50 100.00
keymgr_sideload_aes 24.740s 0.000us 50 50 100.00
keymgr_sideload_otbn 28.250s 0.000us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 30.550s 0.000us 50 50 100.00
lc_disable 50 50 100.00
keymgr_lc_disable 7.040s 0.000us 50 50 100.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 9.560s 0.000us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 64.630s 0.000us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 25.640s 0.000us 50 50 100.00
sync_async_fault_cross 49 50 98.00
keymgr_sync_async_fault_cross 16.640s 0.000us 49 50 98.00
stress_all 48 50 96.00
keymgr_stress_all 347.780s 0.000us 48 50 96.00
intr_test 50 50 100.00
keymgr_intr_test 1.210s 0.000us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.310s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 5.250s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 5.250s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.420s 0.000us 5 5 100.00
keymgr_csr_rw 1.800s 0.000us 20 20 100.00
keymgr_csr_aliasing 12.210s 0.000us 5 5 100.00
keymgr_same_csr_outstanding 3.450s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.420s 0.000us 5 5 100.00
keymgr_csr_rw 1.800s 0.000us 20 20 100.00
keymgr_csr_aliasing 12.210s 0.000us 5 5 100.00
keymgr_same_csr_outstanding 3.450s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 20.090s 0.000us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_tl_intg_err 8.450s 0.000us 20 20 100.00
keymgr_sec_cm 20.090s 0.000us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 6.200s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 6.200s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 6.200s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 6.200s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 15.430s 0.000us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 20.090s 0.000us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 20.090s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 8.450s 0.000us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 6.200s 0.000us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 84.630s 0.000us 50 50 100.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_csr_rw 1.800s 0.000us 20 20 100.00
keymgr_random 54.840s 0.000us 50 50 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_csr_rw 1.800s 0.000us 20 20 100.00
keymgr_random 54.840s 0.000us 50 50 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_csr_rw 1.800s 0.000us 20 20 100.00
keymgr_random 54.840s 0.000us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
keymgr_lc_disable 7.040s 0.000us 50 50 100.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 25.640s 0.000us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 25.640s 0.000us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 54.840s 0.000us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 12.810s 0.000us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.090s 0.000us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.090s 0.000us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 20.090s 0.000us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 22.290s 0.000us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 50 50 100.00
keymgr_lc_disable 7.040s 0.000us 50 50 100.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 20.090s 0.000us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.090s 0.000us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 20.090s 0.000us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 22.290s 0.000us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 22.290s 0.000us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 20.090s 0.000us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 22.290s 0.000us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.090s 0.000us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 22.290s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 31 50 62.00
keymgr_stress_all_with_rand_reset 23.880s 0.000us 31 50 62.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 43320241496690577244611396194453280520116093833343555494364461927131476330593 337
UVM_ERROR @ 1350390968 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1350390968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 9347857743600183602849842311645915673994927533580807987074573898880680036701 282
UVM_ERROR @ 247471987 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 247471987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 30489429405638291791518773126530199542386946838565544717636794139665921835797 251
UVM_ERROR @ 465110656 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 465110656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 26161777065651691803564391379924540695407554616962557467030160493096780774953 252
UVM_ERROR @ 267968257 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 267968257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 846329129396773658569846784225397833695595717673959328877137487386956506612 361
UVM_ERROR @ 431060074 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 431060074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 109527120391061349562086489638454696224430055716331489882839881295327020393793 150
UVM_ERROR @ 242557324 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 242557324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 106492105456149077072269988376259924862068135475321426394560790350657432425647 173
UVM_ERROR @ 938848239 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 938848239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 29299703668857500845186045496298768323277796265128572947409532683945132082747 102
UVM_ERROR @ 511828040 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 511828040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 97379852945704047098476689805123983082024619478832998832923944575729817083757 885
UVM_ERROR @ 648484338 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 648484338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 92711885851434745399643523935068786432672716194453231887548931405343501295224 794
UVM_ERROR @ 621219488 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 621219488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 103733889665166452228851677466315205239605109534686947104379567909636221421525 197
UVM_ERROR @ 445852847 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 445852847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 98858282508426056845087341234918538015080206503136591271512643342182544092133 298
UVM_ERROR @ 493228995 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 493228995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 36610238593473911147875066560118661318293547459704724805550076887405897366524 679
UVM_ERROR @ 213137030 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 213137030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 26311212931440854657381554684034992024839369826103808579126685094862523928976 191
UVM_ERROR @ 111597509 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 111597509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 68420566469213146422084895088128898115444999598460878863220358775705556183944 158
UVM_ERROR @ 997084652 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 997084652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 45080781127112453307061382799886684221302824808764916492692612837520324003225 232
UVM_ERROR @ 124982144 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 124982144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 113026655030022296229259919214374351775506005235134703125505379800629897492343 455
UVM_ERROR @ 2064805737 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2064805737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 47229918748145052884897331709142755860032177970828609385812787476408617632819 318
UVM_ERROR @ 663887731 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 663887731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Attestation Aes
keymgr_stress_all 89509725714178672334501768812752505987546650501339974327462640935999064971564 3985
UVM_ERROR @ 823329208 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (711986446759117756801931552182858964782796381723048228553672254915945424806938599085912901254564839009242203214861994742899656410198464036154379860654212 [0xd981e04a621536a20ce47836138322e342e0ffe327b2bd76e55e6e2630dc8ed63c94b9813c6985e056dd15ce5c57d94a5370f8810df5e5756b92cc237ab3884] vs 711986446759117756801931552182858964782796381723048228553672254915945424806938599085912901254564839009242203214861994742899656410198464036154379860654212 [0xd981e04a621536a20ce47836138322e342e0ffe327b2bd76e55e6e2630dc8ed63c94b9813c6985e056dd15ce5c57d94a5370f8810df5e5756b92cc237ab3884]) AES key at state StDisabled for Attestation Aes
UVM_INFO @ 823329208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_stress_all_with_rand_reset 66248113499095597596038601555879083169831623814275255080701059662303072650149 440
UVM_ERROR @ 256199895 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 256199895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 99361129705406457267600298119998277986438086365354261517185231646324118638671 2439
UVM_ERROR @ 1387924982 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 1387924982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_sideload 50931863785257584068305386481714517998992475602032989565323327016462927221535 124
UVM_ERROR @ 18565721 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 18565721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received!
keymgr_sync_async_fault_cross 6730407188878785549402547382901955832778638955046510929068380045022298693689 178
UVM_ERROR @ 616165273 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
UVM_INFO @ 616165273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---