Simulation Results: kmac/unmasked

 
22/03/2026 00:11:46 DVSim: v1.16.0 sha: 2a81083 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.59 %
  • code
  • 92.34 %
  • assert
  • 97.90 %
  • func
  • 96.54 %
  • line
  • 97.70 %
  • branch
  • 96.04 %
  • cond
  • 94.41 %
  • toggle
  • 100.00 %
  • FSM
  • 73.55 %
Validation stages
V1
100.00%
V2
98.69%
V2S
99.80%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 62.030s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.490s 0.000us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.490s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 15.310s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 10.030s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.080s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.490s 0.000us 20 20 100.00
kmac_csr_aliasing 10.030s 0.000us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.070s 0.000us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.940s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3825.180s 0.000us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 892.300s 0.000us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2002.900s 0.000us 5 5 100.00
kmac_test_vectors_sha3_256 2063.730s 0.000us 5 5 100.00
kmac_test_vectors_sha3_384 31.000s 0.000us 5 5 100.00
kmac_test_vectors_sha3_512 924.220s 0.000us 5 5 100.00
kmac_test_vectors_shake_128 2010.150s 0.000us 5 5 100.00
kmac_test_vectors_shake_256 272.690s 0.000us 5 5 100.00
kmac_test_vectors_kmac 2.340s 0.000us 5 5 100.00
kmac_test_vectors_kmac_xof 2.440s 0.000us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 368.120s 0.000us 50 50 100.00
app 50 50 100.00
kmac_app 326.860s 0.000us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 188.420s 0.000us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 285.200s 0.000us 50 50 100.00
error 50 50 100.00
kmac_error 429.220s 0.000us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 23.430s 0.000us 50 50 100.00
sideload_invalid 39 50 78.00
kmac_sideload_invalid 131.280s 0.000us 39 50 78.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 46.890s 0.000us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 44.110s 0.000us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 85.030s 0.000us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 42.610s 0.000us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2187.800s 0.000us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.120s 0.000us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.330s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.810s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.810s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.490s 0.000us 5 5 100.00
kmac_csr_rw 1.490s 0.000us 20 20 100.00
kmac_csr_aliasing 10.030s 0.000us 5 5 100.00
kmac_same_csr_outstanding 2.950s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.490s 0.000us 5 5 100.00
kmac_csr_rw 1.490s 0.000us 20 20 100.00
kmac_csr_aliasing 10.030s 0.000us 5 5 100.00
kmac_same_csr_outstanding 2.950s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.640s 0.000us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.640s 0.000us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.640s 0.000us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.640s 0.000us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 5.720s 0.000us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_sec_cm 44.340s 0.000us 5 5 100.00
kmac_tl_intg_err 5.230s 0.000us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.230s 0.000us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 42.610s 0.000us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 62.030s 0.000us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 368.120s 0.000us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.640s 0.000us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 44.340s 0.000us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 44.340s 0.000us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 44.340s 0.000us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 62.030s 0.000us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 42.610s 0.000us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 44.340s 0.000us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 302.400s 0.000us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 62.030s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
kmac_stress_all_with_rand_reset 214.900s 0.000us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 61398670327602410341190320983168540820259065708081878317101041984312341267883 273
UVM_ERROR @ 1231541212 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 1231541212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 31879595300284368973753907273026269640609977553282937262900477130537193861376 266
UVM_ERROR @ 9863593674 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 9863593674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 103565501542736280035336657502512762900454356443197196662402930854776763242261 104
UVM_ERROR @ 3172112710 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3172112710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 91780293626671347321969933696931185576685007706941200579832507581682529202698 106
UVM_ERROR @ 3230414661 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3230414661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 83209977267514474369397794840635153132065073798021207738376669607407001113699 126
UVM_ERROR @ 20703800252 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 20703800252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 73841992393146077550331141760087953966857437245477849323760542247196073869362 96
UVM_ERROR @ 1128093436 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1128093436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 80945381262739741241591484343825300627494890165599917943397618115206776232110 80
UVM_FATAL @ 10025313968 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb91b7000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10025313968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 11455227739039213271276209862843975212601788562123253508225832596359777299564 80
UVM_FATAL @ 10131337146 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc7cbc000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10131337146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 110899232396573554342425840675322335885587818644997138865764812425536410448559 80
UVM_FATAL @ 10143183958 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7e3d1000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10143183958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)
kmac_sideload_invalid 21009888581961652785641310801862596978259165973460633350744549507439404595471 85
UVM_FATAL @ 10152487258 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xaaeb2000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10152487258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 6019407250293378010794093149008649827434328811515253018922873410754219781717 85
UVM_FATAL @ 10135288571 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf4e3e000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10135288571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
kmac_sideload_invalid 72128972802711624503147469115224971528118647793156290294343514382392570682228 85
UVM_FATAL @ 10090208900 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3c005000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10090208900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)
kmac_sideload_invalid 5790022515479738538574025653095463468104475351455026914606864432357987499867 91
UVM_FATAL @ 10137969130 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf9f10000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10137969130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 109541599814284476786203804517913387828450019640948319643586934601707169252254 79
UVM_FATAL @ 10019582423 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x49ec0000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10019582423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 34242634853396222093410574810202164750214871333625838633875042297928590291338 78
UVM_FATAL @ 10090919593 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd49bb000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10090919593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 79893277570548109900917409619582020855114567747679908853256690617730201367548 78
UVM_FATAL @ 10008667333 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x41348000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10008667333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14)
kmac_sideload_invalid 57654773695693069359847530930772071955043675014605050042288640797244244401029 94
UVM_FATAL @ 10443943082 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6ff1a000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10443943082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 438280977110900780844860290098962149123446200283075129883095371898825155179 259
UVM_ERROR @ 113245850 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (2555393414 [0x98503586] vs 3610711141 [0xd7371465]) Regname: kmac_reg_block.prefix_6.prefix_0 reset value: 0x0
UVM_INFO @ 113245850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---