Simulation Results: lc_ctrl/volatile_unlock_enabled

 
22/03/2026 00:11:46 DVSim: v1.16.0 sha: 2a81083 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.20 %
  • code
  • 86.21 %
  • assert
  • 94.13 %
  • func
  • 96.26 %
  • line
  • 97.24 %
  • branch
  • 94.21 %
  • cond
  • 81.84 %
  • toggle
  • 89.54 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
98.99%
V2S
100.00%
V3
48.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 5.690s 0.000us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.130s 0.000us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.230s 0.000us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.400s 0.000us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.280s 0.000us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.950s 0.000us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.230s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 1.280s 0.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 10.940s 0.000us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 18.580s 0.000us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.220s 0.000us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.840s 0.000us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 13.030s 0.000us 50 50 100.00
lc_errors 47 50 94.00
lc_ctrl_errors 12.820s 0.000us 47 50 94.00
security_escalation 256 260 98.46
lc_ctrl_state_failure 13.030s 0.000us 50 50 100.00
lc_ctrl_prog_failure 4.840s 0.000us 50 50 100.00
lc_ctrl_errors 12.820s 0.000us 47 50 94.00
lc_ctrl_security_escalation 11.350s 0.000us 50 50 100.00
lc_ctrl_jtag_state_failure 70.830s 0.000us 20 20 100.00
lc_ctrl_jtag_prog_failure 16.840s 0.000us 20 20 100.00
lc_ctrl_jtag_errors 72.230s 0.000us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_csr_hw_reset 2.620s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.680s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 42.310s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 14.700s 0.000us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.710s 0.000us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 6.010s 0.000us 10 10 100.00
lc_ctrl_jtag_alert_test 1.740s 0.000us 10 10 100.00
lc_ctrl_jtag_smoke 10.720s 0.000us 20 20 100.00
lc_ctrl_jtag_state_post_trans 33.340s 0.000us 20 20 100.00
lc_ctrl_jtag_prog_failure 16.840s 0.000us 20 20 100.00
lc_ctrl_jtag_errors 72.230s 0.000us 19 20 95.00
lc_ctrl_jtag_access 26.120s 0.000us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 29.220s 0.000us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 16.880s 0.000us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.530s 0.000us 50 50 100.00
stress_all 48 50 96.00
lc_ctrl_stress_all 433.810s 0.000us 48 50 96.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.690s 0.000us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.120s 0.000us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.120s 0.000us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.130s 0.000us 5 5 100.00
lc_ctrl_csr_rw 1.230s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 1.280s 0.000us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.010s 0.000us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.130s 0.000us 5 5 100.00
lc_ctrl_csr_rw 1.230s 0.000us 20 20 100.00
lc_ctrl_csr_aliasing 1.280s 0.000us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.010s 0.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 3.310s 0.000us 20 20 100.00
lc_ctrl_sec_cm 11.100s 0.000us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.310s 0.000us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 18.580s 0.000us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 13.030s 0.000us 50 50 100.00
lc_ctrl_sec_cm 11.100s 0.000us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 13.030s 0.000us 50 50 100.00
lc_ctrl_sec_cm 11.100s 0.000us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 13.030s 0.000us 50 50 100.00
lc_ctrl_sec_cm 11.100s 0.000us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 13.030s 0.000us 50 50 100.00
lc_ctrl_sec_cm 11.100s 0.000us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 13.030s 0.000us 50 50 100.00
lc_ctrl_sec_cm 11.100s 0.000us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 13.030s 0.000us 50 50 100.00
lc_ctrl_sec_cm 11.100s 0.000us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 13.030s 0.000us 50 50 100.00
lc_ctrl_sec_cm 11.100s 0.000us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 13.030s 0.000us 50 50 100.00
lc_ctrl_sec_cm 11.100s 0.000us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 11.350s 0.000us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 10.940s 0.000us 50 50 100.00
lc_ctrl_jtag_state_post_trans 33.340s 0.000us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 14.870s 0.000us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 14.870s 0.000us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 14.120s 0.000us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 13.050s 0.000us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 13.050s 0.000us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 24 50 48.00
lc_ctrl_stress_all_with_rand_reset 141.470s 0.000us 24 50 48.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all 66413008963327439747738043536148552619875614993846242126090700684958975417261 6837
UVM_ERROR @ 21320492390 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 21320492390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 11830614564690317286987657603220119175219072646969139650839837301573977068657 2270
UVM_ERROR @ 1393701860 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1393701860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 19820479888952985919413435455592030564237147189819634327244202400852602115532 581
UVM_ERROR @ 66692075 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 66692075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 49204310243554007614280157527791237726577233051724798982097288567595050704494 8379
UVM_ERROR @ 17655793973 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 17655793973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 15233864369777839698762471986252623631116748339646196604071903130446009970114 5269
UVM_ERROR @ 7859999066 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7859999066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 106474210669930423768080190829719340088733337915972423906973610092487316132453 528
UVM_ERROR @ 113969831 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 113969831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 38244781188263404507349399851587172815985280869565714668455070235457277030540 2757
UVM_ERROR @ 349132148 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 349132148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 83360244661032903155522110954986397605589556873202893213465967057582578276847 11816
UVM_ERROR @ 3322217215 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3322217215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 27979745117965724196194249332782963238032835683557055703261789339494913460157 3063
UVM_ERROR @ 2433335947 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2433335947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65490101899282480405123849198700406270516187593404438258967314156165674488100 2248
UVM_ERROR @ 12454857573 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12454857573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 109982331540287027125594158105355273877161429799832302359299465729125630115925 6014
UVM_ERROR @ 1463289889 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1463289889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108657808533442202020380603230834866480869284505463073755686471548069434380358 5420
UVM_ERROR @ 2684646720 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2684646720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 49017406040121645856397867625695975592217404591846607937143865852306190149204 5330
UVM_ERROR @ 2127055089 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2127055089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 39438784733949168023725000611038366625784897610774527692090175929278372645660 3285
UVM_ERROR @ 12762079383 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12762079383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 57176343506846384222581396902416362541650397099773650854847994779115165803154 1621
UVM_ERROR @ 8505344276 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8505344276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98262998565877253814481298505685610661156744253924718512587544509124602639706 2013
UVM_ERROR @ 1018571787 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1018571787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 107539994891150158045125419996402603270248096279136065453449062821186232162926 806
UVM_ERROR @ 478369406 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 478369406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 79043338557745029497872133933218246295484657270973912357770775612684874610122 2191
UVM_ERROR @ 3401198951 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3401198951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 23812286522241018980446121095280038959650197541150824173278383676970513006500 992
UVM_ERROR @ 1456771858 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1456771858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98112699145933597688431953198938123581708376556153186195171402904435640411648 7268
UVM_ERROR @ 27113488665 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 27113488665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 110520303287856438948099333619171216377452906087695338570081022697123344047289 709
UVM_ERROR @ 6024023313 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6024023313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 101980370263944753725183549034044718851964487049301272908426501294354378160675 1597
UVM_ERROR @ 6305416622 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6305416622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 61099204661697664297913623633264806053788953021820121613360456450896029619298 3510
UVM_ERROR @ 3825183121 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3825183121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 17172441603663812148928870874700034443382608028993421497505638571548918744612 2201
UVM_ERROR @ 12868218911 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12868218911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16684045296571257297238443124354698432766884584784727293700992334181564692 5139
UVM_ERROR @ 3497822902 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3497822902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 23752655868363208679082122766357108067006165581372679304956582918319201841528 9671
UVM_ERROR @ 8560972113 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8560972113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108952538714838215723227748528616706509696761297272332905481829977823461189658 166
UVM_ERROR @ 1550154456 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1550154456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 6511482615815970264454482129533264223268712842770990018039269791512581133759 199
UVM_ERROR @ 407536668 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 407536668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 76832169618383438170830749198438356098967371355319863761943519377712265788323 5231
UVM_ERROR @ 2475816003 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2475816003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 28500899449057307766034070141419549607919404235974508621757664558390915124582 929
UVM_ERROR @ 3428411870 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3428411870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 3545188543505725027805640843581090594563173168951268713726675932966317687830 21127
UVM_ERROR @ 5660668344 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 5660668344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 73594329033890006444568000405942845622821143528336254775547879561319145593388 15583
UVM_ERROR @ 3627778061 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 3627778061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---